COP8SAA716M8/NOPB National Semiconductor, COP8SAA716M8/NOPB Datasheet - Page 36

IC MCU OTP 8BIT 1K 16-SOIC

COP8SAA716M8/NOPB

Manufacturer Part Number
COP8SAA716M8/NOPB
Description
IC MCU OTP 8BIT 1K 16-SOIC
Manufacturer
National Semiconductor
Series
COP8™ 8SAr
Datasheet

Specifications of COP8SAA716M8/NOPB

Core Processor
COP8
Core Size
8-Bit
Speed
10MHz
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
12
Program Memory Size
1KB (1K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Package
16SOIC W
Family Name
COP8
Maximum Speed
10 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Interface Type
SPI
Number Of Timers
1
Maximum Clock Frequency
10 MHz
Data Ram Size
64 B
Number Of Programmable I/os
16
Height
2.3 mm
Length
10.5 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.6 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
*COP8SAA716M8
*COP8SAA716M8/NOPB
COP8SAA716M8

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11.0 MICROWIRE/PLUS
MICROWIRE/PLUS is a serial SPI compatible synchronous
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with MICROWIRE/PLUS
or SPI peripherals (i.e. A/D converters, display drivers, EE-
PROMs etc.) and with other microcontrollers which support
the MICROWIRE/PLUS or SPI interface. It consists of an
8-bit serial shift register (SIO) with serial data input (SI),
serial data output (SO) and serial shift clock (SK). Figure 24
shows a block diagram of the MICROWIRE/PLUS logic.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift clock
is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table 9 details the
different clock rates that may be selected.
Where t
C
SL1
0
0
1
is the instruction cycle clock
TABLE 9. MICROWIRE/PLUS
Master Mode Clock Select
SL0
0
1
x
2 x t
4 x t
8 x t
FIGURE 24. MICROWIRE/PLUS Application
C
C
C
SK Period
36
11.1 MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 24 shows how
two microcontroller devices and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
The SIO register should only be loaded when the SK clock is
in the idle phase. Loading the SIO register while the SK clock
is in the active phase, will result in undefined data in the SIO
register.
Setting the BUSY flag when the input SK clock is in the
active phase while in the MICROWIRE/PLUS is in the slave
mode may cause the current SK clock for the SIO shift
register to be narrow. For safety, the BUSY flag should only
be set when the input SK clock is in the idle phase.
11.1.1 MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. In the slave mode, the shift clock
stops after 8 clock pulses. Table 10 summarizes the bit
settings required for Master mode of operation.
WARNING
DS012838-32

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