R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 267
R5F21256SNFP#U0
Manufacturer Part Number
R5F21256SNFP#U0
Description
IC R8C MCU FLASH 32K 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21256SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21256SNFP#U0R5F21256SNFP#ES
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.96
Bits TSTART0 and TSTART1
in TRDSTR register
TRDGRB0 register
TRDGRD0 register
TRDSR1 register
TRDSR0 register
TRDSR0 register
TRDIOD0 output
TRDIOC0 output
TRDIOB0 output
Feb 29, 2008
IMFA bit in
IMFB bit in
UDF bit in
Count source
Value in TRDi register
Operating Example of Complementary PWM Mode
0000h
m+1
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
The above applies under the following conditions:
Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase)
1
0
1
0
1
0
1
0
m
n
p
Initial output “H”
Initial output “H”
Page 248 of 485
Transfer (when bits CMD1 to CMD0 are set to 11b)
Active level “L”
n+1
n
n+1-p
m+2-p
n
p
m-p-n+1
phase active level
Set to 0 by a program
Width of normal-
(m-p-n+1) × 2
Set to 0 by a program
Dead
time
p
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRD0 register
Width of counter-phase active level
Transfer (when bits CMD1 to CMD0
are set to 10b)
Value in TRD0 register
n
Value in TRD1 register
Modify with a program
(n+1-p) × 2
Following data
n+1-p
Set to 0 by a program
FFFFh
Set to
14. Timers
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