R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 91
R5F21256SNFP#U0
Manufacturer Part Number
R5F21256SNFP#U0
Description
IC R8C MCU FLASH 32K 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21256SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21256SNFP#U0R5F21256SNFP#ES
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
9.
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/24 Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/25 Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations.
However, only following SFRs are connected with the 16-bit bus:
Timer RD: registers TRDi (i = 0,1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, data flash, even address
byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is accessed at a time.
Table 9.1
Table 9.2
Table 9.3
SFR
ROM/RAM
SFR/Data flash
Program ROM/RAM
Bus
Even address
Even address
Word access
Word access
Odd address
Byte access
Odd address
Byte access
Access Area
Access Area
Area
Feb 29, 2008
Bus Cycles by Access Space of the R8C/24 Group
Bus Cycles by Access Space of the R8C/25 Group
Access Units and Bus Operations
CPU clock
CPU clock
CPU clock
CPU clock
Address
Address
Address
Address
Data
Data
Data
Data
Page 72 of 485
2 cycles of CPU clock
1 cycle of CPU clock
2 cycles of CPU clock
1 cycle of CPU clock
SFR, data flash
Odd
Even
Bus Cycle
Bus Cycle
Data
Data
Even
Odd
Even+1
Odd+1
Data
Data
Data
Data
CPU clock
CPU clock
CPU clock
CPU clock
Address
Address
Address
Address
Data
Data
Data
Data
ROM (program ROM), RAM
Odd
Even
Odd
Even
Data
Data
Data
Data
Even+1
Odd+1
Data
Data
9. Bus
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