R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 140

IC R8C/27 MCU FLASH 32LQFP

R5F21272SDFP#U0

Manufacturer Part Number
R5F21272SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Quantity
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Part Number:
R5F21272SDFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
R5F21272SDFP#U0R5F21272SDFP#V2
Manufacturer:
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Part Number:
R5F21272SDFP#U0R5F21272SDFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 12.8
Figure 12.9
Address
12.1.6.7
m−4
m−3
m−2
m−1
m+1
m
Stack state before interrupt request
is acknowledged
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used
NOTE:
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
MSB
Previous stack contents
Previous stack contents
Sep 26, 2008
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Saving a Register
Stack
Stack State Before and After Acknowledgement of Interrupt Request
Register Saving Operation
Address
NOTE:
[SP]−5
[SP]−4
[SP]−3
[SP]−2
[SP]−1
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
1. When executing software number 32 to 63 INT instructions,
[SP]
After registers are saved, the SP content is [SP] minus 4. When executing software
number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is
ISP.
this SP is specified by the U flag. Otherwise it is ISP.
FLGH
Page 121 of 453
LSB
Stack
PCM
FLGL
PCL
[SP]
SP value before
interrupt is generated
PCH
Sequence in which
order registers are
saved
Completed saving
registers in four
operations.
(3)
(4)
(1)
(2)
Saved, 8 bits at a time
Address
m−4
m−3
m−2
m−1
m
m+1
Stack state after interrupt request
is acknowledged
MSB
Previous stack contents
Previous stack contents
FLGH
FLGL
PCM
PCL
Stack
PCH
PCM
PCL
FLGH
FLGL
PCH
: 4 High-order bits of PC
: 8 Middle-order bits of PC
: 8 Low-order bits of PC
: 4 High-order bits of FLG
: 8 Low-order bits of FLG
(1)
LSB
with a single instruction.
PCH
PCM
PCL
FLGH
FLGL
[SP]
New SP value
: 4 High-order bits of PC
: 8 Middle-order bits of PC
: 8 Low-order bits of PC
: 4 High-order bits of FLG
: 8 Low-order bits of FLG
12. Interrupts

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