R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 151

IC R8C/27 MCU FLASH 32LQFP

R5F21272SDFP#U0

Manufacturer Part Number
R5F21272SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
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Manufacturer:
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
As with other maskable interrupts, the timer RC interrupt, clock synchronous serial I/O with chip select interrupt,
and I
However, since each interrupt source is generated by a combination of multiple interrupt request sources, the
following differences from other maskable interrupts apply:
Refer to chapters of the individual peripheral functions (14.3 Timer RC, 16.2 Clock Synchronous Serial I/O with
Chip Select (SSU) and 16.3 I
Refer to 12.1.6 Interrupt Control for the interrupt control register.
• When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable
• When either bits in the status register or bits in the enable register corresponding to bits in the status register, or
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is
• When multiple bits in the enable register are set to 1, determine by the status register which request source
interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
both, are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is not
acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set
to 0 even if 0 is written to the IR bit.
Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set each bit in the
status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the
status register to 0.
set to 1, the IR bit remains 1.
causes an interrupt.
2
C bus interface interrupt are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL.
Sep 26, 2008
Page 132 of 453
2
C bus Interface) for the status register and enable register.
12. Interrupts

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