R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 157

IC R8C/27 MCU FLASH 32LQFP

R5F21272SDFP#U0

Manufacturer Part Number
R5F21272SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21272SDFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21272SDFP#U0R5F21272SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21272SDFP#U0R5F21272SDFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 13.3
Watchdog Timer Reset Register
Watchdog Timer Start Register
Count Source Protection Mode Register
b7
NOTES:
b7
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
2.
1.
2.
0 0 0
Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
Write 0 before w riting 1 to set the CSPRO bit to 1.
0 cannot be set by a program.
Sep 26, 2008
0
0
Registers WDTR, WDTS, and CSPR
0
b0
b0
0
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.
The default value of the w atchdog timer is 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.
The w atchdog timer starts counting after a w rite instruction to this register.
Bit Symbol
(b6-b0)
CSPRO
Symbol
Symbol
Symbol
WDTR
WDTS
CSPR
Page 138 of 453
Reserved Bits
Count Source Protection Mode
Select Bit
Address
Address
000Dh
000Eh
(2)
Address
Bit Name
001Ch
Function
Function
Set to 0.
0 : Count source protection mode disabled
1 : Count source protection mode enabled
After Reset
After Reset
Undefined
Undefined
After Reset
Function
00h
(1)
(1)
(2)
13. Watchdog Timer
WO
WO
RW
RW
RW
RW
RW

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