R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 316

IC R8C/27 MCU FLASH 32LQFP

R5F21272SDFP#U0

Manufacturer Part Number
R5F21272SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21272SDFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Part Number:
R5F21272SDFP#U0R5F21272SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
R5F21272SDFP#U0R5F21272SDFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.28
IIC bus Status Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
6.
7.
Each bit is set to 0 by reading 1 before w riting 0.
This flag is enabled in slave receive mode of the I
When tw o or more master devices attempt to occupy the bus at nearly the same time, if the I
monitors the SDA pin and the data w hich the I
bus is occupied by the another master.
The NACKF bit is enabled w hen the ACKE bit in the ICIER register is set to 1 (w hen the receive acknow ledge bit is
set to 1, transfer is halted).
The RDRF bit is set to 0 w hen reading data from the ICDRR register.
Bits TEND and TDRE are set to 0 w hen w riting data to the ICDRT register.
When accessing the ICSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Sep 26, 2008
b3 b2 b1
ICSR Register
b0
Bit Symbol
Symbol
NACKF
STOP
RDRF
TEND
TDRE
(7)
ICSR
ADZ
AAS
AL
Page 297 of 453
General call address
recognition flag
Slave address recognition
flag
Arbitration lost
flag/overrun error flag
Stop condition detection
flag
No acknow ledge detection
flag
Receive data register
full
Transmit end
Transmit data empty
(1,5)
(1)
(1)
(1,4)
Address
Bit Name
00BCh
(1,6)
(1,2)
2
C bus Interface transmits is different, the AL flag is set to 1 and the
(1,6)
2
C bus format.
(1)
When the general call address is detected, this flag
is set to 1.
This flag is set to 1 w hen the first frame follow ing
start condition matches bits SVA0 to SVA6 in the
SAR register in slave receive mode. (Detect the
slave address and generate call address)
When the I
that arbitration has been lost in master mode. In the
follow ing cases, this flag is set to 1.
This flag indicates an overrun error w hen the clock
synchronous format is used.
In the follow ing case, this flag is set to 1.
When the stop condition is detected after the frame
is transferred, this flag is set to 1
When no acknow ledge is detected from the receive
device after transmission, this flag is set to 1
When receive data is transferred from in registers
ICDRS to ICDRR , this flag is set to 1
When the 9th clock cycle of the SCL signal in the I
bus format occurs w hile the TDRE bit is set to 1, this
flag is set to 1.
This flag is set to 1 w hen the final bit of the transmit
frame is transmitted in the clock synchronous format.
In the follow ing cases, this flag is set to 1.
• Data is transferred from registers ICDRT to ICDRS
• When setting the TRS bit in the ICCR1
• When generating the start condition
• When changing from slave receive mode to
• When the internal SDA signal and SDA pin
• When the last bit of the next data item is
• When the start condition is detected and the
and the ICDRT register is empty
register to 1 (transmit mode)
(including retransmit)
slave transmit mode
level do not match at the rise of the SCL signal
in master transmit mode
SDA pin is held “H” in master transmit/receive mode
received w hile the RDRF bit is set to 1
2
C bus format is used, this flag indicates
16. Clock Synchronous Serial Interface
After Reset
0000X000b
Function
2
(3)
C bus Interface
2
C
RW
RW
RW
RW
RW
RW
RW
RW
RW

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