R5F21254SDFP#U0 Renesas Electronics America, R5F21254SDFP#U0 Datasheet - Page 272
R5F21254SDFP#U0
Manufacturer Part Number
R5F21254SDFP#U0
Description
IC R8C MCU FLASH 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21254SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21254SDFP#U0R5F21254SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.2.00 Oct 17, 2005
REJ09B0001-0200
5.3 Interrupt Sequence
The interrupt sequence — the operations performed from the instant an interrupt is accepted to the instant
the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle.
If an interrupt occurs during execution of the SMOVB, SMOVF, SSTR, or RMPA instruction, the processor
temporarily suspends the instruction being executed and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the operations listed below. Figure 5.3.1 shows the
interrupt sequence execution time.
After the interrupt sequence is completed, the processor resumes executing instructions from the starting
address of the interrupt routine.
Note 1: This register cannot be accessed by the user.
Chapter 5
Figure 5.3.1 Interrupt Sequence Executing Time
(1) The CPU obtains the interrupt information (the interrupt number and interrupt request level) by reading
(2) The FLG register is saved as it was immediately before the start of the interrupt sequence in a tempo-
(3) The I flag, the D flag, and the U flag in the FLG register are set as follows:
(4) The contents of the temporary register
(5) The PC is saved in the stack area.
(6) The interrupt priority level of the accepted instruction is set in IPL.
(7) The first address of the interrupt routine set to the interrupt vector is set in the PC.
A d d r e s s b u s
C P U c l o c k
• The I flag is cleared to 0 (interrupts disabled)
• The D flag is cleared to 0 (single-step interrupt disabled)
•The U flag is cleared to 0 (ISP specified)
However, the U flag status does not change when the INT instruction for software interrupt numbers 32 to
63 is executed.
D a t a b u s
address 00000
issued).
rary register
R D
W R
1
N o t e : U n d e f i n e d p a r t s d i f f e r a c c o r d i n g t o t h e s t a t e s o f t h e q u e u e b u f f e r .
Interrupts
I f t h e q u e u e b u f f e r i s i n a s t a t e w h e r e a n i n s t r u c t i o n c a n b e a c c e p t e d , a r e a d
c y c l e i s g e n e r a t e d .
1
2
A d d r e s s
0 0 0 0 0
within the CPU.
i n f o r m a t i o n
16
I n t e r r u p t
page 252 of 263
1 6
. Then, the IR bit corresponding to the interrupt is set to 0 (interrupt not requested
3
4
5
U n d e f i n e d
U n d e f i n e d
Undefined
6
7
1
are saved within the CPU in the stack area.
8
S P - 2
9
c o n t e n t s
S P - 2
S P - 1
1 0
contents
SP-1
SP-4
11
c o n t e n t s
S P - 4
1 2
SP-3
contents
SP-3
13
V E C
1 4
c o n t e n t s
V E C
15
V E C + 1
c o n t e n t s
V E C + 1
1 6
5.3 Interrupt Sequence
1 7
V E C + 2
c o n t e n t s
V E C + 2
1 8
1 9
PC
2 0
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