MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 159

IC MCU 60K FLASH 8MHZ 32-LQFP

MC908GZ60CFJE

Manufacturer Part Number
MC908GZ60CFJE
Description
IC MCU 60K FLASH 8MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GZ60CFJE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
CAN, ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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12.13.4 MSCAN08 Bus Timing Register 1
SAMP — Sampling
TSEG22–TSEG10 — Time Segment
1. In this case PHASE_SEG1 must be at least 2 time quanta.
Freescale Semiconductor
TSEG13
1. This setting is not valid. Please refer to
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in
Table
number of time quanta (T
0
0
0
0
1
.
.
1 = Three samples per bit
0 = One sample per bit
12-8. The bit time is determined by the oscillator frequency, the baud rate prescaler, and the
TSEG12
0
0
0
0
1
Address:
.
.
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
The CBTR1 register can only be written if the SFTRES bit in the MSCAN08
module control register is set.
Reset:
Read:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
TSEG11
$0503
SAMP
0
0
1
1
1
Bit 7
.
.
0
Figure 12-19. Bus Timing Register 1 (CBTR1)
Bit time =
q
) clock cycles per bit as shown in
TSEG10
TSEG22
(1)
0
1
0
1
1
.
.
6
0
Table 12-8. Time Segment Values
Table 12-4
f
Pres value
MSCANCLK
TSEG21
2 T
3T
16 T
1 T
Segment 1
4 T
5
0
q
q
q
Time
q
Cycles
for valid settings.
Cycles
q
Cycle
Cycles
.
.
Cycles
NOTE
NOTE
TSEG20
(1)
(1)
(1)
4
0
• number of time quanta
TSEG13
3
0
TSEG22
Table
0
0
1
.
.
Programmer’s Model of Control Registers
TSEG12
2
0
12-4).
TSEG21
0
0
1
.
.
TSEG11
1
0
TSEG20
0
1
1
.
.
TSEG10
Bit 0
0
1 T
2 T
Segment 2
8T
q
q
Time
q
Cycle
Cycles
Cycles
.
.
(1)
159

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