MC908AP64CFAE Freescale Semiconductor, MC908AP64CFAE Datasheet - Page 63

• Manufacturer Part Number: MC908AP64CFAE
• Description: IC MCU 64K 8MHZ SPI 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP64CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• Package: 48LQFP
• Family Name: HC08
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
BSR rel
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC
CLI
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
CPHX #opr
CPHX opr
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
DAA
Source
Form
Branch to Subroutine
Compare and Branch if Equal
Clear Carry Bit
Clear Interrupt Mask
Clear
Compare A with M
Complement (One’s Complement)
Compare H:X with M
Compare X with M
Decimal Adjust A
Operation
Table 4-1. Instruction Set Summary
MC68HC908AP Family Data Sheet, Rev. 4
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
(H:X) – (M:M + 1)
PC ← (PC) + rel
SP ← (SP) – 1
Description
M ← $00
M ← $00
M ← $00
M ← $00
A ← $00
X ← $00
H ← $00
(A) – (M)
(X) – (M)
C ← 0
I ← 0
(A)
10
V H I N Z C
U – – o o o INH
– – – – – – REL
– – – – – –
– – – – – 0 INH
– – 0 – – – INH
0 – – 0 1 –
0 – – o o 1
o – – o o o
o – – o o o
o – – o o o
Effect on
CCR
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
9E6F
9EE1
9ED1
9EE3
9ED3
9E61
9E63
AD
9A
8C
A1
B1
C1
D1
E1
A3
B3
C3
D3
E3
31
41
51
61
71
98
3F
4F
5F
6F
7F
F1
33
43
53
63
73
65
75
F3
72
Opcode Map
rr
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
ii ii+1
dd
ii
dd
hh ll
ee ff
ff
ff
ee ff
63
4
5
4
4
5
4
6
1
2
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
3
4
2
3
4
4
3
2
4
5
2