HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 21
HD64F3664FPV
Manufacturer Part Number
HD64F3664FPV
Description
IC H8/3664 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of HD64F3664FPV
Core Size
16-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300H
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
No. Of I/o's
29
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD64F3664FPV
Manufacturer:
MURATA
Quantity:
34 000
Company:
Part Number:
HD64F3664FPV
Manufacturer:
HD
Quantity:
465
Company:
Part Number:
HD64F3664FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3664FPV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 146
Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 147
Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 148
Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 148
Section 12 Timer W
Figure 12.1 Timer W Block Diagram ......................................................................................... 151
Figure 12.2 Free-Running Counter Operation ............................................................................ 160
Figure 12.3 Periodic Counter Operation..................................................................................... 161
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 161
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 162
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 162
Figure 12.7 Input Capture Operating Example........................................................................... 163
Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 163
Figure 12.9 PWM Mode Example (1) ........................................................................................ 164
Figure 12.10 PWM Mode Example (2) ...................................................................................... 165
Figure 12.11 Buffer Operation Example (Output Compare) ...................................................... 165
Figure 12.12 PWM Mode Example
Figure 12.13 PWM Mode Example
Figure 12.14 Count Timing for Internal Clock Source ............................................................... 168
Figure 12.15 Count Timing for External Clock Source.............................................................. 168
Figure 12.16 Output Compare Output Timing ........................................................................... 169
Figure 12.17 Input Capture Input Signal Timing........................................................................ 169
Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 170
Figure 12.19 Buffer Operation Timing (Compare Match).......................................................... 170
Figure 12.20 Buffer Operation Timing (Input Capture) ............................................................. 171
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 171
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 172
Figure 12.23 Timing of Status Flag Clearing by CPU................................................................ 172
Figure 12.24 Contention between TCNT Write and Clear ......................................................... 173
Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 174
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 177
Figure 13.2 Watchdog Timer Operation Example...................................................................... 180
Section 14 Serial Communication Interface3 (SCI3)
Figure 14.1 Block Diagram of SCI3 ........................................................................................... 182
Figure 14.2 Data Format in Asynchronous Communication ...................................................... 195
(TOB, TOC, and TOD = 0: initial output values are set to 0)................................ 166
(TOB, TOC, and TOD = 1: initial output values are set to 1)................................ 167
Occur at the Same Timing ..................................................................................... 175
Rev. 5.00, 03/04, page xxi of xxviii
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