HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 266

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit
12. Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from low
15.4.3
The data buffer of the I
ICDRS. However, if the completion of receiving the last data is delayed, there will be a contention
between the instruction to issue a stop condition and the SCl clock output to receive the next data,
and may generate unnecessary clocks or fix the output level of the SDA line as low. The switch
timing of the ACKB bit in the ICSR register should be controlled because the acknowledge bit
does not return acknowledgement after receiving the last data in master mode. These problems can
be avoided by using the WAIT function. Follow the flowchart shown below.
Rev. 5.00, 03/04, page 238 of 388
(master output)
(master output)
(slave output)
User processing
Note: * Data write timing in ICDR
ICDR writing
prohibited
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
is 0). When there is data to be transmitted, go to the step [9] to continue next transmission.
When the slave device has not acknowledged (ACKB bit is set to 1), operate the step [12] to
end transmission.
to high when SCL is high, and generates the stop condition.
SDA
SCL
SDA
ICDR
IRTR
IRIC
Start condition generation
*
Master Receive Operation
[4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
Figure 15.5 Master Transmit Mode Operation Timing Example
[5]
Normal
operation
2
C module can receive data consecutively since it consists of ICDRR and
[6] ICDR write
Bit 7
1
Address + R/W
Bit 6
2
(MLS = WAIT = 0)
Bit 5
[6] IRIC clearance
3
Slave address
Slave address
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
R/W
8
[7]
9
A
[9] ICDR write
[9] IRIC clearance
Bit 7
Data 1
1
Data 1
Bit 6
2