M30260F8AGP#U7A Renesas Electronics America, M30260F8AGP#U7A Datasheet - Page 110
M30260F8AGP#U7A
Manufacturer Part Number
M30260F8AGP#U7A
Description
IC M16C/26A MCU FLASH 64K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Specifications of M30260F8AGP#U7A
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
M30260F8AGP#U7AM30260F8AGP#D3
Manufacturer:
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Quantity:
10 000
Part Number:
M30260F8AGP#U7AM30260F8AGP#D5
Manufacturer:
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11.5 Channel Priority and DMA Transfer Timing
. v
J
1
Figure 11.5.1 DMA Transfer by External Factors
0
6
2
9
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de-
tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU
clock), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA
requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC
operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 11.5.1
shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultanelously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requsts cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 11.5.1, occurs more than one time, the DAMS bit is set to "0" as soon
as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
C
0 .
B
2 /
0
0
2
6
0
F
A
2
e
0 -
b
INT0
DMA0
request bit
INT1
G
CPU clock
DMA0
DMA1
CPU
DMA1
request bit
1 .
An example where DMA requests for external causes are detected active at the same
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0
, 5
0
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0
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1
6
page 91
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6
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6
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2
9
2 /
6
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1
6
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Obtainment
of the bus
right
11. DMAC
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