M30260F8AGP#U7A Renesas Electronics America, M30260F8AGP#U7A Datasheet - Page 121
M30260F8AGP#U7A
Manufacturer Part Number
M30260F8AGP#U7A
Description
IC M16C/26A MCU FLASH 64K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Specifications of M30260F8AGP#U7A
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M30260F8AGP#U7AM30260F8AGP#D3
Manufacturer:
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Quantity:
10 000
Part Number:
M30260F8AGP#U7AM30260F8AGP#D5
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M30260F8AGP#U7AM30260F8AGP#U3
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M
R
R
e
E
1
. v
J
6
Figure 12.1.2.1.1. Two-phase Pulse (A phase and B phase) and the Z Phase
0
C
2
9
2 /
0 .
B
0
0
6
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
2
A
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “0000
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.1.2.1.1
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
0
F
2
G
e
0 -
b
o r
1 .
2
u
Timer A3
0
TA3
(A phase)
TA3
(B phase)
Count source
INT2
(Z phase)
NOTE:
, 5
0
p
1. This timing diagram is for the case where the POL bit in the INT2IC register is set to “1” (= rising edge).
2
(
OUT
IN
0
M
0
(1)
1
7
6
C
_______
page 102
2 /
6
, A
M
1
f o
6
C
3
2 /
2
9
6
m
, B
M
1
m+1
6
C
2 /
6
Input equal to or greater than one clock cycle
of count source
) T
1
2
3
4
16
” to the TA3 register and setting
_______
5
12. Timer
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