M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 117
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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R
R
M
e
E
3
. v
J
2
Figure 10.7 Stack States
0
C
10.6.6 Saving a Register
10.6.7 Restoration from Interrupt Routine
1
9
0 .
8 /
B
In the interrupt sequence, the FLG register and PC are saved to the stack.
After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32
bits, are saved to the stack. Figure 10.7 shows stack states before and after an interrupt request is
acknowledged.
Other important registers are saved by program at the beginning of an interrupt routine. The PUSHM
instruction can save several registers
Refer to 10.4 High-Speed Interrupt for the high-speed interrupt.
NOTE:
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC before the
interrupt sequence is performed, which have been saved to the stack, are automatically restored. The pro-
gram, executed before an interrupt request was acknowledged, starts running again. Refer to 10.4 High-
Speed Interrupt for the high-speed interrupt.
Restore registers saved by program in an interrupt routine by the POPM instruction or others before the
REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt
sequence by the REIT or FREIT instruction.
Stack state before an interrupt request is acknowledged
0
0
0
2
Address
1. Can be selected from the R0, R1, R2, R3, A0, A1, SB and FB registers.
7
G
N
1
o
o r
0 -
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
. v
u
1
0
0
p
, 1
0
MSB
2
0
0
Content of
previous stack
Content of
previous stack
5
The Stack
Page 96
f o
3
3
LSB
0
(1)
[SP]
SP value before
an interrupt is
generated
in the register bank used.
Stack state after an interrupt request is acknowledged
Address
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
MSB
Content of
previous stack
Content of
previous stack
The Stack
FLG
PC
PC
FLG
PC
00
M
16
L
H
L
H
LSB
[SP]
New SP value
10. Interrupts
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