M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 135
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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M
R
R
e
E
3
. v
J
2
Figure 12.4 DCT0 to DCT3 Registers and DRC0 to DRC3 Registers
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
0 -
DMAi Transfer Count Register
DMAi Transfer Count Reload Register
. v
b15
b15
u
NOTES:
1
NOTES:
p
0
0
, 1
0
1. Use the LDC instruction to set the DRC0 and DRC1 registers.
2. To set the DRC2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R2
3. To set the DRC3 register, set the B flag to "1" and set R3 register. Use the MOV instruction to set the
1. When the DCTi register is set to "0000
2. Use the LDC instruction to set the DCT0 and DCT1 registers.
3. To set the DCT2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R0
4. To set the DCT3 register, set the B flag to "1" and set R1 register. Use the MOV instruction to
2
register. Use the MOV instruction to set the R2 register.
R3 register.
register. Use the MOV instruction to set the R0 register.
set the R1 register.
0
0
b8 b7
5
b8 b7
Page 114
b0
b0
f o
3
Set the number of transfers
Set the number of transfers
3
0
Symbol
DCT0
DCT1
DCT2(bank1;R0)
DCT3(bank1;R1)
Symbol
DRC0
DRC1
DRC2(bank1;R2)
DRC3(bank1;R3)
(2)
(2)
(1)
(1)
16
(i=0 to 3)
", no data transfer occurs regardless of a DMA request.
(3)
(4)
(2)
(3)
Function
Function
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(i=0 to 3)
0000
0000
After Reset
XXXX
XXXX
0000
0000
After Reset
XXXX
XXXX
0000
0000
Setting Range
Setting Range
16
16
16
16
16
16
to FFFF
to FFFF
16
16
16
16
16 (1)
16
RW
RW
RW
RW
12. DMAC
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