M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 222
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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2
Table 16.20 Register Settings in Special Mode 2
0
i=0 to 4
C
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
0 -
. v
u
1
0
0
p
, 1
0
7 to 0
7 to 0
OER
7 to 0
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS
UiRRM
UiLCH, SCLKSTPB Set to "0"
7 to 0
7 to 0
SSE
CKPH
DINC
NODC
ERR
7 to 5
7 to 0
2
0
0
5
Bit
Page 201
f o
Set transmit data
Received data can be read
Overrun error flag
Set bit rate
Set to "001
Set to "0" in master mode or "1" in slave mode
Set to "0"
Select count source for the UiBRG register
Disabled because the CRD bit is set to "1"
Transfer register empty flag
Set to "1"
Select the output format of the TxDi pin
Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in
the UiSMR3 register
Select either LSB first or MSB first
Set to "1" to enable data transmission and reception
Transfer buffer empty flag
Set to "1" to enable data reception
Reception complete flag
Select what causes the UARTi transmit interrupt to be generated
Set to "1" to enable continuous receive mode
Set to "00
Set to "00
Set to "1"
Clock phase can be set by the combination of the CKPH bit and the CKPOL bit
in the UiC0 register
Set to "0" in master mode or "1" in slave mode
Set to "0"
Fault error flag
Set to "000
Set to "00
3
3
0
16
16
16
2
2
"
"
"
"
"
Function
16. Serial I/O (Special Function)
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