M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 311
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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M
R
R
e
E
3
. v
J
Switching Characteristics
Table 23.20 Memory Expansion Mode and Microprocessor Mode
2
NOTES:
d t
h t
h t
h t
d t
h t
h t
h t
d t
h t
d t
h t
d t
h t
d t
h t
d t
h t
d t
0
C
1
9
B (
B (
(
(
B (
B (
(
(
B (
B (
B (
B (
(
(
B (
B (
A (
A (
z
0 .
8 /
S
R
W
R
W
D
W
(V
B
1. Values can be obtained from the following equations, according to BCLK frequency.
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
(
3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
4. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
C
C
D
C
C
D
C
C
C
C
- B
C
C
D
L
R
t
t
t
t
t
y
R
R
R
h(RD – AD)
h(RD – CS)
0
h(WR – AD)
h(WR – CS)
h(WR – DB)
0
E
0
L
L
A -
L
L
-
L
L
L
L
L
L
A -
D
t
m
A -
-
W
-
CC
C
t
A -
d(AD – ALE)
2
K
K
- K
- K
C
- K
- K
- K
- K
D
K
K
t
A -
d(DB – WR)
h(ALE – AD)
D
L
) S
A -
A -
A -
A -
D
) S
R
) B
7
G
b
D
N
C
C
R
R
W
W
) E
)
D
)
)
1
l o
D
D
) S
) S
D
D
L
L
)
= 4.2 to 5.5V, V
R
R
)
o
o r
) E
) E
)
)
)
)
0 -
)
)
. v
(when accessing an external memory space with the multiplexed bus)
u
1
p
0
0
R
R
D
D
A
A
A
A
C
C
C
C
W
W
A
A
A
A
A
=
=
, 1
0
=
=
=
D
D
d
d
d
d
h
h
h
h
a
a
L
L
L
L
d
R
R
=
=
d
d
d
d
a t
a t
E
E
E
E
d
p i
p i
p i
p i
2
=
S
S
e r
e r
e r
e r
e r
0
S
S
S -
S -
S -
S -
S
S
S
S
g i
g i
O
O
0
g i
g i
s s
s s
s s
s s
s s
g i
g i
g i
g i
e
e
e
e
5
n
n
u
u
f
f
f
f
f
n
n
(BCLK)
(BCLK)
(BCLK)
(BCLK)
(BCLK)
e l
e l
e l
e l
l a
l a
p t
p t
n
n
n
n
f
O
O
O
O
l a
l a
O
f
(BCLK)
f
l a
l a
l a
l a
t c
t c
t c
t c
(BCLK)
Page 290
(BCLK)
10 X n
t u
t u
10 X m
10 X m
u
u
u
u
O
O
u
10 X n
10
10
10
10
10
O
O
p t
p t
p t
p t
O
O
O
O
p t
S
S
S
S
u
u
D
H
9
9
u
u
9
SS
u
u
u
u
t u
t u
t u
t u
g i
g i
g i
g i
p t
p t
t u
9
9
9
9
9
X 2
X 2
X 2
X 2
X 2
p t
p t
e
o
p t
p t
p t
p t
n
n
n
n
X 2
t u
t u
a l
d l
X 2
X 2
t u
t u
D
H
H
H
F
= 0V at Topr = –20 to 85
l a
l a
l a
l a
t u
t u
t u
t u
y
o l
e
o
o
o
i T
D
H
D
H
O
O
O
O
i T
a l
d l
d l
d l
D
H
D
H
t a
e
o
m
– 10
– 10
– 10
– 10
– 10
e
o
u
u
u
u
e
o
e
o
y
a l
d l
m
– 20
f o
– 25
i T
i T
i T
a l
d l
e
S
– 10
p t
p t
p t
p t
a l
d l
a l
d l
i T
y
e
P
y
m
m
m
i T
a t
(
y
y
3
t u
t u
t u
t u
i T
i T
W
m
i T
i T
(
a
m
i T
3
e
e
e
t r
W
i T
i T
m
a r
m
m
m
e
R
0
D
H
H
H
e
m
B (
(
(
i T
[ns]
[ns]
[ns]
[ns]
[ns]
m
m
R
e
m
R
W
e
o
o
o
e
e
e
s
e
[ns] (if external bus cycle is a + b , n= a)
[ns] (if external bus cycle is a + b , m= (bx2)-1)
m
a l
d l
d l
d l
e
e
C
[ns] (if external bus cycle is a + b , n= a)
D
t e
s
a t
R
B (
a (
L
y
a t
e
B (
a (
r e
i T
i T
i T
n
s
d
K
s
C
n
a t
i T
d
d
d
a t
C
m
m
m
L
d
r a
s
d
e r
n
m
L
K
n
r a
a t
e
e
e
e r
d
) d
K
d
s s
e
) d
n
r a
B (
(
(
s
s s
r a
R
W
s
a t
d
) d
a t
s
C
D
) d
r a
R
n
s
a t
L
n
d
a t
) d
s
K
n
s
d
r a
a t
a t
n
d
r a
s
) d
d
r a
n
o
n
a t
) d
r a
d
C unless otherwise specified)
d
) d
r a
n
r a
) d
d
) d
) d
r a
) d
See Figure 23.1
M
e
C
a
o
s
n
u
d
e r
t i
o i
m
n
e
t n
23. Electrical Characteristics
(
(
(
(
(
(
(
(
N
N
N
N
N
N
N
N
M
o
o
o
o
o
o
o
o
3 -
3 -
5 -
5 -
5 -
e t
e t
e t
e t
e t
e t
e t
e t
i
. n
S
V
) 1
) 1
) 1
) 1
) 2
) 1
) 3
) 4
a t
CC1
n
d
a
d r
=V
M
1
1
1
1
1
8
a
8
8
8
8
8
. x
CC2
=5V
U
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
t i
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