M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 314

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

R
R
M
e
E
3
. v
J
2
Figure 23.3 V
0
1
C
9
0 .
B
8 /
0
0
0
2
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
7
N
G
1
o
0 -
[ Write Timing ] (2 +2 Bus Cycle)
o r
[ Read Timing ] (2 +2 Bus Cycle)
CSi
ADi
BHE
RD
CSi
ADi
BHE
WR,WRL,
WRH
BCLK
ALE
ADi
/DBi
BCLK
ALE
ADi
/DBi
. v
NOTE:
NOTE:
1
u
0
1. Varies with operation frequency:
0
p
2. Varies with operation frequency:
, 1
0
t
t
t
t
t
d(AD-ALE)
h(ALE-AD)
h(RD-AD)
ac2(RD-DB)
ac2(AD-DB)
2
t
(if external bus cycle is a + b , n=a)
t
(if external bus cycle is a + b , n=a)
t
t
t
(if external bus cycle is a + b , m=(b x 2)-1)
CC1
d(AD-ALE)
h(ALE-AD)
h(WR-AD)
h(WR-CS)
d(DB-WR)
0
0
5
=V
18ns.max
t
d(BCLK-ALE)
t
18ns.max
d(BCLK-ALE)
=(tcyc/2-10)ns.min, t
Page 293
=(tcyc/2 x n-20)ns.min (if external bus cycle is a + b , n=a)
=(tcyc/2 x n-10)ns.min (if external bus cycle is a + b , n=a)
=(tcyc/2-10)ns.min,
=(tcyc/2-10)ns.min, t
=(tcyc/2 x m-25)ns.min
CC2
=(tcyc/2 x p-35)ns.max (if external bus cycle is a + b , p={(a+b-1) x 2}+1)
=(tcyc/2 x m-35)ns.max (if external bus cycle is a + b , m=(b x 2)-1)
=(tcyc/2 x n - 20)ns.min
=(tcyc/2 x n -10)ns.min
t
d(BCLK-CS)
18ns.max
t
t
t
18ns.max
18ns.max
d(BCLK-AD)
18ns.max
d(BCLK-CS)
d(BCLK-AD)
t
t
d(AD-ALE)
=5V Timing Diagram (2)
d(AD-ALE)
t
ac2(AD-DB)
f o
(1)
(2)
3
3
(1)
0
h(RD-CS)
Address
Address
h(WR-DB)
t
h(BCLK-ALE)
t
h(BCLK-ALE)
-5ns.min
-5ns.min
=(tcyc/2-10)ns.min
t
h(ALE-AD)
=(tcyc/2-10)ns.min
t
h(ALE-AD)
(2)
(1)
t
t
d(BCLK-RD)
d(BCLK-WR)
18ns.max
t
dz(RD-AD)
18ns.max
8ns.max
t
ac2(RD-DB)
tcyc
tcyc
t
d(DB-WR)
tcyc=
Measurement Conditions:
• V
• Input high and low voltage:
• Output high and low voltage:
(1)
t
t
su(DB-BCLK)
h(BCLK-WR)
f
CC1
(BCLK)
t
Data output
h(BCLK-RD)
-5ns.min
(2)
-5ns.min
10
V
V
=V
IH
OH
9
=2.5V, V
Data input
CC2
=2.0V, V
t
h(WR-CS)
=4.2 to 5.5V
26ns.min
t
0ns.min
h(RD-DB)
Vcc
t
23. Electrical Characteristics
IL
h(RD-CS)
t
OL
h(WR-DB)
=0.8V
t
t
h(RD-AD)
h(WR-AD)
=0.8V
(2)
1
=Vcc
(1)
(2)
t
h(BCLK-AD)
(1)
(2)
2
t
-3ns.min
t
=5V
t
h(BCLK-CS)
-3ns.min
Address
-3ns.min
-3ns.min
h(BCLK-CS)
h(BCLK-AD)
Address