MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Price
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MC9S12E128CPVE
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MC9S12E128
MC9S12E64
MC9S12E32
Data Sheet
HCS12
Microcontrollers
MC9S12E128V1
Rev. 1.07
10/2005
freescale.com

MC9S12E128CPVE Summary of contents

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MC9S12E128 MC9S12E64 MC9S12E32 Data Sheet HCS12 Microcontrollers MC9S12E128V1 Rev. 1.07 10/2005 freescale.com ...

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MC9S12E128 Data Sheet MC9S12E64 & MC9S12E32 covers MC9S12E128V1 Rev. 1.07 10/2005 ...

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... Date Level October 10, 2005 01.07 New Data Sheet Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. 4 Description MC9S12E128 Data Sheet, Rev. 1.07 ...

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... Chapter 16 Debug Module (DBGV1 473 Chapter 17 Interrupt (INTV1 505 Chapter 18 Multiplexed External Bus Interface (MEBIV3 513 Chapter 19 Module Mapping Control (MMCV4 543 Appendix A Electrical Characteristics 563 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Appendix C Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 Freescale Semiconductor MC9S12E128 Data Sheet, Rev. 1.07 5 ...

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... MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... PM4 / RXD2 — Port M I/O Pin 1.4.24 PM3 — Port M I/O Pin 1.4.25 PM1 / DAO1 — Port M I/O Pin 1.4.26 PM0 / DAO2 — Port M I/O Pin 1.4.27 PP[5:0] / PW0[5:0] — Port P I/O Pins [5: Freescale Semiconductor Chapter 1 MC9S12E128 Data Sheet, Rev. 1.07 7 ...

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... Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.7.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.8.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.8.2 Pseudo Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.8.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.8.4 Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.9 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.9.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.9.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.10 Recommended Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.4.5 Pull Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.4.6 Polarity Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.4.7 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 3.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 3.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Freescale Semiconductor Chapter 2 Chapter 3 MC9S12E128 Data Sheet, Rev. 1.07 9 ...

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... Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.5.3 Power-On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.6.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.6.3 Self-Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10 Chapter 4 — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 167 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 6.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 6.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 6.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Freescale Semiconductor Chapter 5 Oscillator (OSCV2) — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 202 Chapter 6 MC9S12E128 Data Sheet, Rev. 1.07 11 ...

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... Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 8.4.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.4.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 8.4.6 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 8.4.7 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 8.5.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 8.5.2 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 12 Chapter 7 Chapter 8 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 10.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Freescale Semiconductor Chapter 9 Chapter 10 Inter-Integrated Circuit (IICV2) MC9S12E128 Data Sheet, Rev. 1.07 13 ...

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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 12.2.1 PWM5 — Pulse Width Modulator Channel 5 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 12.2.2 PWM4 — Pulse Width Modulator Channel 4 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 12.2.3 PWM3 — Pulse Width Modulator Channel 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 14 Chapter 11 Chapter 12 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 13.6.1 Channel [7:4] Interrupt (C[7:4] 438 13.6.2 Pulse Accumulator Input Interrupt (PAOVI 438 13.6.3 Pulse Accumulator Overflow Interrupt (PAOVF 438 13.6.4 Timer Overflow Interrupt (TOF 438 Freescale Semiconductor Chapter 13 Timer Module (TIM16B4CV1) MC9S12E128 Data Sheet, Rev. 1.07 15 ...

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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 15.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 15.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 16 Chapter 14 — Regulator Output2 (PLL 442 Chapter 15 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 17.4.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 17.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.6.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 Freescale Semiconductor Chapter 16 Debug Module (DBGV1) Chapter 17 Interrupt (INTV1) MC9S12E128 Data Sheet, Rev. 1.07 17 ...

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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 19.4.1 Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 19.4.2 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 19.4.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 18 Chapter 18 Chapter 19 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... A.6.5 ATD Accuracy — 3.3V Range 592 A.7 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 A.7.1 DAC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 B.1 64-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 B.2 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 B.3 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 Freescale Semiconductor Appendix A Electrical Characteristics Appendix B Package Information Appendix C Ordering Information MC9S12E128 Data Sheet, Rev ...

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... MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... Multiplexed External Bus Interface (MEBI) • Wake-Up interrupt inputs — port bits available for wake up interrupt function with digital filtering • Memory Options — 32K, 64K or 128K Byte Flash EEPROM — 2K Byte RAM Freescale Semiconductor MC9S12E128 Data Sheet, Rev. 1.07 21 ...

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... Real Time interrupt — Clock Monitor — Pierce or low current Colpitts oscillator — Phase-locked loop clock frequency multiplier — Self Clock mode in absence of external clock — Low power 0.5 to 16Mhz crystal oscillator reference clock 22 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

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... Special Test Mode (Freescale use only) — Special Peripheral Mode (Freescale use only) • Low power modes — Stop Mode — Pseudo Stop Mode — Wait Mode Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) TM mode MC9S12E128 Data Sheet, Rev. 1.07 23 ...

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... KWAD8 PAD8 AN8 KWAD9 PAD9 AN9 KWAD10 PAD10 AN10 KWAD11 PAD11 AN11 AN12 KWAD12 PAD12 AN13 KWAD13 PAD13 KWAD14 PAD14 AN14 KWAD15 AN15 PAD15 DAC0 DAO0 PM0 PM1 DAC1 DAO1 PM3 RXD2 PM4 TXD2 PM5 SDA PM6 PM7 SCL Freescale Semiconductor ...

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... Pulse Width Modulator 8-bit 6 channels (PWM) 0x0200–0x023F Pulse Width Modulator with Fault 15-bit 6 channels (PMF) 0x0240–0x027F Port Integration Module (PIM) 0x0280–0x03FF Reserved Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Table 1-1. Device Register Map Overview Module MC9S12E128 Data Sheet, Rev. 1.07 Figure 1-2, ...

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... MC9S12E128 Data Sheet, Rev. 1.07 1K Register Space Mappable to any 2K Boundary 8K Bytes RAM Mappable to any 8K Boundary 0.5K, 1K Protected Sector 16K Fixed Flash EEPROM 16K Page Window eight * 16K Flash EEPROM Pages 16K Fixed Flash EEPROM 2K, 4K 16K Protected Boot Sector BDM (If Active) Freescale Semiconductor ...

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... The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000–$03FF: Register Space $0000–$0FFF: 4K RAM (only 3K RAM visible $0400–$0FFF) Figure 1-3. MC9S12E64 User Configurable Memory Map Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) $0000 $03FF ...

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... MC9S12E128 Data Sheet, Rev. 1.07 1K Register Space Mappable to any 2K Boundary 2K Bytes RAM Mappable to any 2K Boundary 0.5K, 1K Protected Sector 16K Fixed Flash EEPROM 16K Page Window two * 16K Flash EEPROM Pages 16K Fixed Flash EEPROM 2K, 4K 16K Protected Boot Sector BDM (If Active) Freescale Semiconductor ...

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... W R 0x0008 PORTE Bit 0x0009 DDRE Bit 0x000A PEAR NOACCE W R 0x000B MODE MODC W R 0x000C PUCR PUPKE W R 0x000D RDRIV RDPK 0x000E EBICTL 0x000F Reserved W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit PIPOE NECLK LSTRE 0 MODB MODA ...

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... Bit 3 Bit 2 Bit 1 Bit RAMHAL EE11 EEON EXSTR0 ROMHM ROMON Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 ADR2 ADR1 ADR0 INT6 INT4 INT2 INT0 Bit 3 Bit 2 Bit 1 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 0 LVDS LVIE LVIF Freescale Semiconductor 0 0 ...

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... R Bit 15 0x0022 — W DBGTBL R Bit 7 0x0023 — W DBGCNT R TBF 0x0024 — W DBGCCX R 0x0025 — W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit 4 ID14 ID13 ID12 ID6 ID5 ID4 Bit 6 Bit 5 Bit 4 0 eep_sw1 eep_sw0 rom_sw0 0 0 Bit 6 Bit 5 Bit 4 ...

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... MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit BKCEN TAGC RWCEN RWAEN RWA RWBEN EXTCMP EXTCMP Bit 3 Bit 2 Bit 1 PIX3 PIX2 PIX1 Bit 3 Bit 2 Bit 1 XAB17 XAB16 XAB15 XAB14 Freescale Semiconductor Bit 0 Bit 8 Bit 0 RWC RWB Bit 8 Bit 0 Bit 8 Bit 0 Bit 0 PIX0 0 Bit 0 Bit 0 ...

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... CFORC W FOC7 R 0x0042 OC7M OC7M7 W R 0x0043 OC7D OC7D7 W R Bit 15 0x0044 TCNT (hi Bit 7 0x0045 TCNT (lo) W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit 4 0 SYN5 SYN4 REFDV3 TOUT6 TOUT5 TOUT4 TOUT3 0 PROF LOCKIF 0 0 LOCKIE PSTP SYSWAI ...

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... TSFRZ TFFCA TOV6 TOV5 TOV4 OL7 OM6 OL6 EDG7A EDG6B EDG6A EDG5B C6I C5I C4I TCRE C6F C5F C4F MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit OM5 OL5 OM4 OL4 EDG5A EDG4B EDG4A PR2 PR1 PR0 Bit 8 Freescale Semiconductor ...

Page 35

... R 0 0x0060 PACTL 0x0061 PAFLG W R 0x0062 PACNT (hi) Bit 0x0063 PACNT (lo) Bit 0x0064 Reserved 0x0065 Reserved 0x0066 Reserved 0x0067 Reserved 0x0068 Reserved 0x0069 Reserved 0x006A Reserved 0x006B Reserved W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit PAEN PAMOD PEDGE ...

Page 36

... Bit 2 Bit Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit WRAP3 WRAP2 WRAP1 WRAP0 ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 ETRIGP ETRIG ASCIE S1C FIFO FRZ1 PRS3 PRS2 PRS1 CC2 CC1 CCF11 CCF10 CCF9 Freescale Semiconductor Bit Bit 0 0 Bit ASCIF FRZ0 PRS0 CA CC0 CCF8 ...

Page 37

... R Bit15 0x009A ATDDR5H W R Bit7 0x009B ATDDR5L W R Bit15 0x009C ATDDR6H W R Bit7 0x009D ATDDR6L W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit 4 CCF6 CCF5 CCF4 CCF3 IEN14 IEN13 IEN12 IEN11 IEN6 IEN5 IEN4 PTAD14 PTAD13 PTAD12 PTAD11 PTAD6 ...

Page 38

... ETRIGSEL and ETRIGCH0–3 bits are available in version V04 of ATD10B16C 38 Bit 6 Bit 5 Bit Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 0 0 MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Freescale Semiconductor ...

Page 39

... IREN W R 0x00D1 SCIBDL SBR7 W R 0x00D2 SCICR1 LOOPS W R 0x00D3 SCICR2 TIE W R TDRE 0x00D4 SCISR1 W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 TNP1 TNP0 SBR12 SBR11 SBR6 SBR5 SBR4 SCISWAI RSRC M TCIE RIE ...

Page 40

... MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit 0 RAF 1 BRK13 TXDIR Bit 3 Bit 2 Bit 1 Bit 0 CPHA SSOE LSBFE 0 SPISWAI SPC0 0 SPR2 SPR1 SPR0 Bit0 Bit 3 Bit 2 Bit 1 Bit 0 ADR2 ADR1 IBC3 IBC2 IBC1 IBC0 0 0 IBSWAI RSTA 0 SRW RXAK IBIF Freescale Semiconductor ...

Page 41

... SCICR2 TIE W R TDRE 0x00EC SCISR1 0x00ED SCISR2 0x00EE SCIDRH 0x00EF SCIDRL TXPOL and RXPOL are available in version V04 of SCI Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 TNP1 TNP0 SBR12 SBR11 SBR6 SBR5 SBR4 ...

Page 42

... BIT0 BIT3 BIT2 BIT1 BIT0 Bit 3 Bit 2 Bit 1 Bit 0 DJM DSGN DACWAI DACOE BIT3 BIT2 BIT1 BIT0 BIT3 BIT2 BIT1 BIT0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 FDIV2 FDIV1 FDIV0 NV3 NV2 SEC1 SEC0 FPLDIS FPLS1 FPLS0 Freescale Semiconductor ...

Page 43

... W 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet Address Name Bit 7 R 0x0140 TIOS IOS7 0x0141 CFORC W FOC7 R 0x0142 OC7M OC7M7 W R 0x0143 OC7D OC7D7 W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit 4 CCIF PVIOL ACCERR 0 CMDB6 CMDB5 ...

Page 44

... TFFCA TOV6 TOV5 TOV4 OL7 OM6 OL6 EDG7A EDG6B EDG6A EDG5B C6I C5I C4I TCRE C6F C5F C4F MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit Bit Bit OM5 OL5 OM4 OL4 EDG5A EDG4B EDG4A PR2 PR1 PR0 Freescale Semiconductor ...

Page 45

... TC7 (hi) Bit 0x015F TC7 (lo) Bit 0x0160 PACTL 0x0161 PAFLG W R 0x0162 PACNT (hi) Bit 0x0163 PACNT (lo) Bit 0x0164 Reserved 0x0165 Reserved 0x0166 Reserved 0x0167 Reserved 0x0168 Reserved 0x0169 Reserved W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit PAEN PAMOD PEDGE ...

Page 46

... FOC4 OC7M6 OC7M5 OC7M4 OC7D6 OC7D5 OC7D4 TSWAI TSFRZ TFFCA TOV6 TOV5 TOV4 OL7 OM6 OL6 MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit Bit OM5 OL5 OM4 OL4 Freescale Semiconductor ...

Page 47

... R 0 0x0197 Reserved W R 0x0198 TC4 (hi) Bit 0x0199 TC4 (lo) Bit 0x015A TC5 (hi) Bit 0x019B TC5 (lo) Bit 0x019C TC6 (hi) Bit 15 W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit EDG7A EDG6B EDG6A EDG5B C6I C5I C4I TCRE C6F C5F C4F ...

Page 48

... R 0 0x01AB Reserved 0x01AC Reserved 0x01AD Reserved 0x01AE Reserved 0x01AF Reserved W 48 Bit 6 Bit 5 Bit PAEN PAMOD PEDGE MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit 0 CLK1 CLK0 PAOVI PAI 0 0 PAOVF PAIF Bit Bit Freescale Semiconductor ...

Page 49

... PWMSCNTB W R Bit 7 0x01EC PWMCNT0 Bit 7 0x01ED PWMCNT1 Bit 7 0x01EE PWMCNT2 Bit 7 0x01EF PWMCNT3 W 0 Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 0 PWME5 PWME4 PWME3 0 PPOL5 PPOL4 PPOL3 0 PCLK5 PCLK4 PCLK3 PCKB2 PCKB1 PCKB0 ...

Page 50

... PWMSDN PWMIF 0x01FF Reserved W 50 Bit 6 Bit 5 Bit PWMIE PWMLVL PWMRSTRT MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 0 0 PWM5IN PWM5INL PWM5ENA Freescale Semiconductor ...

Page 51

... R 0 0x020E PMFDTMS 0x020F PMFCCTL W R 0x0210 PMFVAL0 Bit 0x0211 PMFVAL0 Bit 0x0212 PMFVAL1 Bit 15 W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit 4 MTG EDGEC EDGEB 0 BOTNEGC TOPNEGC 0 MSK5 MSK4 0 PMFFRZ VLMODE FIE3 FMODE2 FIE2 0 FPINE3 FPINE2 0 FFLAG3 ...

Page 52

... PMFMODA W R 0x0225 PMFMODA Bit Bit 6 Bit 5 Bit LDFQA HALFA Bit Bit MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit LDOKA PWMRIEA PRSCA PWMRFA Bit Bit Bit Bit 0 Freescale Semiconductor ...

Page 53

... W R 0x0231 PMFFQCC 0x0232 PMFCNTC W R 0x0233 PMFCNTC Bit 0x0234 PMFMODC W R 0x0235 PMFMODC Bit 0x0236 PMFDTMC W R 0x0237 PMFDTMC Bit 0x0238 Reserved W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit Bit LDFQB HALFB Bit Bit Bit LDFQC HALFC ...

Page 54

... MC9S12E128 Data Sheet, Rev. 1.07 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 PTT3 PTT2 PTT1 PTT0 PTIT2 PTIT1 PTIT0 DDRT2 DDRT1 DDRT0 RDRT2 RDRT1 RDRT0 PERT2 PERT1 PERT0 PPST2 PPST1 PPST0 PTS3 PTS2 PTS1 PTS0 PTIS2 PTIS1 PTIS0 Freescale Semiconductor ...

Page 55

... R 0 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit 4 DDRS6 DDRS5 DDRS4 DDRS3 RDRS6 RDRS5 RDRS4 RDRS3 PERS6 PERS5 PERS4 PERS3 PPSS6 PPSS5 PPSS4 PPSS3 WOMS6 WOMS5 WOMS4 WOMS3 ...

Page 56

... PPSP2 PPSP1 PPSP0 PTQ2 PTQ1 PTQ0 PTIQ2 PTIQ1 PTIQ0 DDRQ2 DDRQ1 DDRQ0 RDRQ2 RDRQ1 RDRQ0 PERQ2 PERQ1 PERQ0 PPSQ2 PPSQ1 PPSQ0 PTU2 PTU1 PTU0 PTIU2 PTIU1 PTIU0 DDRU2 DDRU1 DDRU0 RDRU2 RDRU1 RDRU0 PERU2 PERU1 PERU0 PPSU2 PPSU1 PPSU0 Freescale Semiconductor ...

Page 57

... PIFAD7 W 0x0280 – 0x03FF Reserved Space Address Name Bit 0x0280– Reserved 0x2FF 0x0300– Unimplemented 0x03FF W Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Bit 6 Bit 5 Bit 4 PTAD14 PTAD13 PTAD12 PTAD11 PTAD6 PTAD5 PTAD4 PTAD3 PTIAD14 PTIAD13 PTIAD12 PTIAD11 PTIAD6 PTIAD5 ...

Page 58

... Table 1-2. Assigned Part ID Numbers Mask Set Number 2L15P shows the read-only values of these registers. Refer to HCS12 Module Table 1-3. Memory Size Registers Device Register name MEMSIZ0 MEMSIZ1 MC9S12E128 Data Sheet, Rev. 1.07 Table 1-2 shows the assigned 1 Part ID 0x5102 Value 0x03 0x80 Freescale Semiconductor ...

Page 59

... IS2/PQ6 22 MODC/TAGHI/BKGD 23 IOC04/PT0 24 IOC05/PT1 25 IOC06/PT2 26 IOC07/PT3 27 IOC14/PT4 28 Signals shown in Bold are not available on the 80-pin package Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) MC9S12E128 112LQFP Figure 1-5. Pin Assignments for 112-LQFP MC9S12E128 Data Sheet, Rev. 1.07 84 VRH 83 VDDA 82 PAD07/AN07/KWAD07 81 PAD06/AN06/KWAD06 80 PAD05/AN05/KWAD05 ...

Page 60

... Signals shown in Bold are not available on the 64-pin package 60 MC9S12E128 80 QFP Figure 1-6. Pin Assignments for 80-QFP MC9S12E128 Data Sheet, Rev. 1.07 VRH 60 VDDA 59 PAD07/AN07/KWAD07 58 PAD06/AN06/KWAD06 57 PAD05/AN05/KWAD05 56 PAD04/AN04/KWAD04 55 PAD03/AN03/KWAD03 54 PAD02/AN02/KWAD02 53 PAD01/AN01/KWAD01 52 PAD00/AN00/KWAD00 51 VSS2 50 VDD2 49 PS7/SS 48 PS6/SCK 47 PS5/MOSI 46 PS4/MISO 45 PS3/TXD1 44 PS2/RXD1 43 PS1/TXD0 42 PS0/RXD0 41 Freescale Semiconductor ...

Page 61

... FAULT0/PQ0 5 FAULT1/PQ1 6 FAULT2/PQ2 7 FAULT3/PQ3 8 VDDX 9 VSSX 10 MODC/BKGD 11 IOC04/PT0 12 IOC05/PT1 13 IOC06/PT2 14 IOC07/PT3 15 IOC14/PT4 16 Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) MC9S12E128 64 QFN Figure 1-7. Pin Assignments for 64-QFN MC9S12E128 Data Sheet, Rev. 1.07 48 VRH 47 VDDA 46 PAD06/AN06/KWAD06 45 PAD04/AN04/KWAD04 44 PAD02/AN02/KWAD02 43 PAD00/AN00/KWAD00 42 VSS2 41 VDD2 40 PS7/SS ...

Page 62

... Port K I/O Pin, External Chip Select Port K I/O Pins, Extended Addresses Port M I/O Pin, IIC SCL signal Port M I/O Pin, IIC SDA signal Port M I/O Pin, SCI2 transmit signal Port M I/O Pin, SCI2 receive signal Port M I/O Pin Port M I/O Pin, DAC1 output Freescale Semiconductor ...

Page 63

... This applies to the following pins: (80QFP): Port A[7:0], Port B[7:0], Port E[6,5,3,2], Port K[7:0], Port U[7:4] (64QFN): Port U[3:0], Port Q[6:4], Port M[3], Port AD[14,11,10,9,7,5,3,1] Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Table 1-4. Signal Properties ...

Page 64

... PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins PB[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:0] pins are not available in the 80 pin package version. 64 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 65

... The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low. PE6 is not available in the 80 pin package version. Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1 ...

Page 66

... PE1 is always an input and can always be read. The PE1 pin is also the IRQ input used for requesting an asynchronous interrupt to the MCU. During reset, the I bit in the condition code register (CCR) is set and any IRQ interrupt is masked until software enables it by clearing the I bit. The IRQ is software 66 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 67

... PAD[15:0] are the analog inputs for the analog to digital converter (ADC). They can also be configured as general purpose digital input or output pin. When enabled as digital inputs or outputs, the PAD[15:0] can Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) MC9S12E128 Data Sheet, Rev. 1.07 ...

Page 68

... PM1 is a general purpose input or output pin. When the Digital to Analog module 1 (DAC1) is enabled the PM1 pin is configured as the analog output DA01 of DAC1. While in reset and immediately out of reset the PM1 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) 68 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 69

... SS. While in reset and immediately out of reset the PS7 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 block description chapter and the SPI block description chapter for information about pin configurations. Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) MC9S12E128 Data Sheet, Rev. 1.07 ...

Page 70

... PS1 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 block description chapter and the SCI block description chapter for information about pin configurations. 70 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 71

... PW1[3:0] outputs. The MODRR register in the Port Integration Module determines if the TIM2 or PWM function is selected. While in reset and immediately out of reset the PU[3:0] pins are configured as a high Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) MC9S12E128 Data Sheet, Rev. 1.07 ...

Page 72

... VDDPLL, VSSPLL — Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. 72 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 73

... All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load. Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Description ...

Page 74

... Table 1-6. Clock Selection Based on PE7 Description Colpitts Oscillator selected Pierce Oscillator/external clock selected MC9S12E128 Data Sheet, Rev. 1.07 HCS12 CORE BDM CPU MEBI MMC INT DBG Flash RAM ATD DAC IIC PIM PMF PWM SCI0, SCI1, SCI2 SPI TIM0, TIM1, TIM2 VREG Freescale Semiconductor ...

Page 75

... For further explanation on the modes refer to the HCS12 MEBI block description chapter. PE7 = XCLKS 1 0 Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Table 1-7. Mode Selection PK7 = ROMON ROMCTL Bit X 1 Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active ...

Page 76

... FLASH. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to 76 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 77

... CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG and VREG block description chapters for detailed information on reset generation. 1.9.1 Vectors Table 1-9 lists interrupt sources and vectors in default order of priority. Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) MC9S12E128 Data Sheet, Rev. 1.07 77 ...

Page 78

... ATDCTL2 (ASCIE) 0xD0 PTADIF (PTADIE) 0xCE PLLCR (LOCKIE) 0xC6 PLLCR (SCMIE) 0xC4 IBCR (IBIE) 0xC0 FCNFG (CCIE, CBEIE) 0xB8 TIE (C4I) 0xB6 TIE (C5I) 0xB4 TIE (C6I) 0xB2 TIE (C7I) 0xB0 TSCR2 (TOI) 0xAE Freescale Semiconductor – – – – – – ...

Page 79

... Resets are a subset of the interrupts featured in system reset are summarized in 1.9.2.1 Reset Summary Table Reset Power-on Reset External Reset Low Voltage Reset Clock Monitor Reset COP Watchdog Reset Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) CCR Mask I-Bit overflow I-Bit edge Reserved I-Bit ...

Page 80

... Refer to the PIM block description chapter for reset configurations of all peripheral module ports. Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. 80 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 81

... C2 VDD2 filter cap (80 QFP only C10 C11 R1 Q1 Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Purpose Type VDD1 filter cap Ceramic X7R Ceramic X7R VDDA filter cap Ceramic X7R VDDR filter cap X7R/tantalum VDDPLL filter cap Ceramic X7R VDDX filter cap ...

Page 82

... Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) VDDX C6 VSSX Figure 1-11. Recommended PCB Layout (112-LQFP) 82 NOTE: Oscillator in Colpitts mode. VSSA VSS1 VSSR VDDR Q1 VSSPLL VDDPLL R1 MC9S12E128 Data Sheet, Rev. 1.07 C3 VDDA VSS2 C2 VDD2 Freescale Semiconductor ...

Page 83

... VDDX C6 VSSX Figure 1-12. Recommended PCB Layout (80-QFP) Freescale Semiconductor Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) NOTE: Oscillator in Colpitts mode. VSS1 VSSR VDDR VSSPLL R1 VDDPLL MC9S12E128 Data Sheet, Rev. 1.07 VSSA C3 VDDA VSS2 C2 VDD2 Q1 83 ...

Page 84

... Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) VDDX C6 VSSX Figure 1-13. Recommended PCB Layout (64-QFN) 84 NOTE: Oscillator in Colpitts mode. VSSA VSS1 VSSR VDDR VSSPLL R1 VDDPLL MC9S12E128 Data Sheet, Rev. 1.07 C3 VDDA VSS2 C2 VDD2 Q1 Freescale Semiconductor ...

Page 85

... Flexible protection scheme to prevent accidental program or erase • Single power supply for Flash program and erase operations • Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor CAUTION MC9S12E128 Data Sheet, Rev. 1.07 85 ...

Page 86

... The FTS128K1 module contains no signals that connect off-chip. 86 Operations”. Flash Interface Command Pipeline cmd1 cmd2 addr1 addr2 data2 data1 Registers Protection Security FCLK Figure 2-1. FTS128K1 Block Diagram MC9S12E128 Data Sheet, Rev. 1.07 Flash Array 64K * 16 Bits sector 0 sector 1 sector 127 Freescale Semiconductor ...

Page 87

... By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top fixed 16 Kbyte pages can be seen twice in the MCU memory map. Freescale Semiconductor Figure 2-2. The HCS12 architecture places the Flash array Table 2-1. Table 2-1. Flash Configuration Field Description ...

Page 88

... Flash Protected Low Sectors Kbytes 0x3E Flash Array 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B Flash Protected High Sectors 0x3F Kbytes 0xFF00–0xFF0F (Flash Configuration Field) Figure 2-2. Flash Memory Map MC9S12E128 Data Sheet, Rev. 1.07 0x3C 0x3D 003E 0x3F Freescale Semiconductor ...

Page 89

... Unpaged (0x3F) 1 Inside Flash block allowed by MCU. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Protectable Protectable Low Range High Range N.A. N.A. 0x4000–0x43FF N.A. 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF N.A. ...

Page 90

... FABHI FABLO FDHI FDLO Figure 2-3. Flash Register Summary MC9S12E128 Data Sheet, Rev. 1.07 Figure 2-3. Detailed descriptions of each FDIV3 FDIV2 FDIV1 NV3 NV2 SEC1 FPHS0 FPLDIS FPLS1 0 BLANK FAIL 0 0 CMDB2 Freescale Semiconductor Bit 0 FDIV0 SEC0 0 0 FPLS0 DONE CMDB0 ...

Page 91

... W Reset Unimplemented or Reserved All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence, indicated Figure 2-5. Freescale Semiconductor FDIV5 FDIV4 FDIV3 Table 2-3. FCLKDIV Field Descriptions ...

Page 92

... DISABLED Table 2-6. Flash Security States SEC[1:0] Status of Security 00 Secured 1 01 Secured 10 Unsecured 11 Secured Preferred SEC state to set MCU to secured state. Section 2.4.3, “Flash Module Figure 2-6. RESERVED1 MC9S12E128 Data Sheet, Rev. 1.07 Table 2-6. If the Flash Security” Freescale Semiconductor ...

Page 93

... R FPOPEN NV6 W Reset F F Figure 2-8. Flash Protection Register (FPROT) The FPROT register is readable in normal and special modes. FPOPEN can only be written from FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until Freescale Semiconductor KEYACC Table 2-7. FCNFG Field Descriptions ...

Page 94

... A mass erase of the whole Flash array is only possible when Table 2-8. FPROT Field Descriptions Description 2-10. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. 2-11. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 95

... Although the protection scheme is loaded from the Flash array after reset allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. Freescale Semiconductor Table 2-9. Flash Protection Function FPHS[0] FPLDIS ...

Page 96

... FPROT register reflect the active protection scenario. Table 2-12. Flash Protection Scenario Transitions From Protection Scenario FPHDIS = 1 FPHDIS = 0 FPLDIS = 0 FPLDIS = Protected Flash Figure 2-9. Flash Protection Scenarios Table 2-12. Any attempt to write an invalid scenario to the To Protection Scenario MC9S12E128 Data Sheet, Rev. 1.07 FPHDIS = 0 FPLDIS = Freescale Semiconductor ...

Page 97

... The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see 0 Command in progress 1 All commands are completed Freescale Semiconductor To Protection Scenario ...

Page 98

... Figure 2-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits and 1 read 0 and are not writable. 98 Table 2-13. FSTAT Field Descriptions Description CMDB5 MC9S12E128 Data Sheet, Rev. 1. CMDB2 CMDB0 Freescale Semiconductor ...

Page 99

... Module Base + 0x0008 Reset 0 0 Figure 2-13. Flash Address High Register (FADDRHI Freescale Semiconductor Table 2-14. FCMD Field Descriptions Description Table 2-15. An attempt to execute any command other than those listed in Section Table 2-15. Valid Flash Command List CMDB NVM Command 0x05 ...

Page 100

... In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 2.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. 100 FABLO FDHI FDLO MC9S12E128 Data Sheet, Rev. 1. Freescale Semiconductor ...

Page 101

... This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000E Reset Unimplemented or Reserved All bits read 0 and are not writable. 2.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1 Figure 2-17. RESERVED3 ...

Page 102

... FCLKDIV determination must take this information into account define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), 102 Figure 2-20. RESERVED6 MC9S12E128 Data Sheet, Rev. 1. Freescale Semiconductor ...

Page 103

... If the FCLKDIV register is written, the bit FDIVLD is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. Freescale Semiconductor 5% = CAUTION MC9S12E128 Data Sheet, Rev ...

Page 104

... PRDIV8=0 (reset) no oscillator_clock 12.8MHz? yes PRDIV8=1 PRDCLK=oscillator_clock PRDCLK=oscillator_clock/8 no PRDCLK[MHz]*(5+Tbus[ s]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ s])) yes FCLK=(PRDCLK)/(1+FDIV[5:0]) yes 1/FCLK[MHz] + Tbus[ s] > 5 AND FCLK > 0.15MHz ? no yes FDIV[5:0] > ALL COMMANDS IMPOSSIBLE MC9S12E128 Data Sheet, Rev. 1.07 ALL COMMANDS IMPOSSIBLE END Freescale Semiconductor ...

Page 105

... Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) MC9S12E128 Data Sheet, Rev. 1.07 ...

Page 106

... FPROT register are set prior to launching the command. A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 106 Table 2-16. Valid Flash Commands Function on Flash Array CAUTION MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 107

... BLANK flag in the FSTAT register will be set if all addresses in the Flash array are verifi erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Figure MC9S12E128 Data Sheet, Rev ...

Page 108

... CBEIF no Set? yes ACCERR/ yes Write: FSTAT register PVIOL Clear ACCERR/PVIOL 0x30 Set? no and Dummy Data Read: FSTAT register no CCIF Set? yes no BLANK Set? yes Flash Array EXIT Erased MC9S12E128 Data Sheet, Rev. 1.07 Flash Array EXIT Not Erased Freescale Semiconductor ...

Page 109

... CBEIF flag in the FSTAT register has been set 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Figure MC9S12E128 Data Sheet, Rev. 1.07 2-23 ...

Page 110

... Write: Flash Address and program Data Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register no CBEIF Set? yes yes Next Word? no Read: FSTAT register no CCIF Set? yes EXIT MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 111

... Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Figure MC9S12E128 Data Sheet, Rev ...

Page 112

... Set? Write: FCLKDIV register Read: FSTAT register CBEIF no Set? yes ACCERR/ yes Write: FSTAT register PVIOL Clear ACCERR/PVIOL 0x30 Set? no and Dummy Data Read: FSTAT register no CCIF Set? yes EXIT MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 113

... Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Figure MC9S12E128 Data Sheet, Rev ...

Page 114

... Write: FSTAT register PVIOL Clear ACCERR/PVIOL 0x30 Set? no Write: Flash Block Address and Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register no CCIF Set? yes EXIT MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 115

... Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL flag is set, the Flash command controller is locked not possible to launch another command until the PVIOL flag is cleared. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) MC9S12E128 Data Sheet, Rev. 1.07 Section 2 ...

Page 116

... Flash array, the MCU will be unsecured. The data must be written to the backdoor key 116 NOTE can be executed. If the MCU is secured and is in special single chip Section 2.3.2.2, “Flash Security Register MC9S12E128 Data Sheet, Rev. 1.07 Section 2.4.5). Freescale Semiconductor ...

Page 117

... FPROT register not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor Chapter 2 128 Kbyte Flash Module (FTS128K1V1) MC9S12E128 Data Sheet, Rev. 1.07 ...

Page 118

... Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) NOTE FLASH INTERRUPT REQUEST Figure 2-26. Flash Interrupt Implementation Section 2.3.2.4, “Flash Configuration Register (FSTAT)”. MC9S12E128 Data Sheet, Rev. 1.07 Local Enable Global (CCR) Mask CBEIE I Bit CCIE I Bit Freescale Semiconductor ...

Page 119

... Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt input with glitch filtering Freescale Semiconductor NOTE MC9S12E128 Data Sheet, Rev. 1.07 119 ...

Page 120

... PW04 PP4 PW05 PP5 RXD PS0 TXD PS1 RXD PS2 TXD PS3 PS4 PS5 SCK PS6 SS PS7 BKGD XIRQ PE0 IRQ PE1 R/W PE2 PE3 ECLK PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 XCS PK6 PK7 Freescale Semiconductor ...

Page 121

... GPIO PB1 ADDR1/DATA1 GPIO PB0 ADDR0/DATA0 GPIO Freescale Semiconductor Chapter 3 Port Integration Module (PIM9E128V1) Description Refer to the MEBI block description chapter Refer to the BDM block description chapter Refer to the MEBI block description chapter Refer to the MEBI block description chapter General-purpose I/O ...

Page 122

... General-purpose I/O Refer to the MEBI block description chapter General-purpose I/O Refer to the MEBI block description chapter General-purpose I/O MC9S12E128 Data Sheet, Rev. 1.07 Pin Function after Reset Refer to the MEBI block description chapter Refer to the MEBI block description chapter Freescale Semiconductor ...

Page 123

... PAD2 AN2 KWAD2 GPIO PAD1 AN1 KWAD1 GPIO PAD0 AN0 KWAD0 GPIO Freescale Semiconductor Chapter 3 Port Integration Module (PIM9E128V1) Description Analog-to-digital converter input channel 15 Keyboard wake-up interrupt 15 General-purpose I/O Analog-to-digital converter input channel 14 Keyboard wake-up interrupt 14 General-purpose I/O Analog-to-digital converter input channel 13 ...

Page 124

... General-purpose I/O PMF current status pin 0 General-purpose I/O PMF fault pin3 General-purpose I/O PMF fault pin 2 General-purpose I/O PMF fault pin 1 General-purpose I/O PMF fault pin 0 General-purpose I/O MC9S12E128 Data Sheet, Rev. 1.07 Pin Function after Reset GPIO GPIO GPIO Freescale Semiconductor ...

Page 125

... IOC2 GPIO PT1 IOC1 GPIO PT0 IOC0 GPIO Freescale Semiconductor Chapter 3 Port Integration Module (PIM9E128V1) Description Serial peripheral interface slave select input/output in master mode, input in slave mode General-purpose I/O Serial peripheral interface serial clock pin General-purpose I/O Serial peripheral interface master out/slave in pin ...

Page 126

... General-purpose I/O Timer 2 channel 7 Pulse-width modulator 1 channel 3 General-purpose I/O Timer 2 channel 6 Pulse-width modulator 1 channel 2 General-purpose I/O Timer 2 channel 5 Pulse-width modulator 1 channel 1 General-purpose I/O Timer 2 channel 4 Pulse-width modulator 1 channel 0 General-purpose I/O MC9S12E128 Data Sheet, Rev. 1.07 Pin Function after Reset GPIO Freescale Semiconductor ...

Page 127

... Port P Reduced Drive Register (RDRP) 0x001C Port P Pull Device Enable Register (PERP) 0x001D Port P Polarity Select Register (PPSP) 0x001E - 0x001F Reserved Freescale Semiconductor Table 3-2 Table 3-2. PIM9HZ256 Memory Map Use MC9S12E128 Data Sheet, Rev. 1.07 Chapter 3 Port Integration Module (PIM9E128V1 standard memory map of port ...

Page 128

... ATDDIEN1 registers do not affect the port AD pins when they are configured as outputs. 128 Use MC9S12E128 Data Sheet, Rev. 1.07 Access R/W R R/W R/W R/W R/W — R/W R R/W R/W R/W R/W R/W — R/W R R/W R/W R/W R/W R/W R/W Freescale Semiconductor ...

Page 129

... I/O register bit (PTADx) reads “1”. If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN0(1) bit is set to 1 (digital input buffer is enabled), a read returns the value of the pin. Freescale Semiconductor 5 4 ...

Page 130

... If the ATDDIEN0(1) bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin. 130 PTIAD13 PTIAD12 PTIAD11 PTIAD5 PTIAD4 PTIAD3 Figure 3-3. Port AD Input Register (PTIAD) MC9S12E128 Data Sheet, Rev. 1. PTIAD10 PTIAD9 PTIAD8 PTIAD2 PTIAD1 PTIAD0 Freescale Semiconductor ...

Page 131

... PTADx returns the value on port AD pin. If the associated ATDDIEN0(1) bit is set to 0 (digital input buffer is disabled), a read on PTADx returns a 1. Field 15:0 Data Direction Port AD DDRAD[15:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor DDRAD13 DDRAD12 DDRAD11 0 ...

Page 132

... Reduced Drive Port AD RDRAD[15:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 132 RDRAD13 RDRAD12 RDRAD11 RDRAD5 RDRAD4 RDRAD3 Table 3-4. RDRAD Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. RDRAD10 RDRAD9 RDRAD8 RDRAD2 RDRAD1 RDRAD0 Freescale Semiconductor ...

Page 133

... This register configures whether a pull- pull-down device is activated on configured input pins pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Field 15:0 Pull Device Enable Port AD PERAD[15:0 0 Pull-up or pull-down device is disabled Pull-up or pull-down device is enabled. Freescale Semiconductor PERAD13 PERAD12 PERAD11 0 0 ...

Page 134

... A pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt generation. 134 PPSAD13 PPSAD12 PPSAD11 PPSAD5 PPSAD4 PPSAD3 Table 3-6. PPSAD Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. PPSAD10 PPSAD9 PPSAD8 PPSAD2 PPSAD1 PPSAD0 Freescale Semiconductor ...

Page 135

... Figure 3-8. Port AD Interrupt Enable Register (PIEAD) Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port AD. Field 15:0 Interrupt Enable Port AD PIEAD[15:0] 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Freescale Semiconductor PIEAD13 PIEAD12 PIEAD11 ...

Page 136

... Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag. 136 PIFAD13 PIFAD12 PIFAD11 PIFAD5 PIFAD4 PIFAD3 NOTE Table 3-8. PIFAD Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. PIFAD10 PIFAD9 PIFAD8 PIFAD2 PIFAD1 PIFAD0 Freescale Semiconductor ...

Page 137

... If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin. 3.3.2.2 Port M Input Register (PTIM PTIM7 PTIM6 W Reset Reserved or Unimplemented Freescale Semiconductor 5 4 PTM5 PTM4 PTM3 TXD2 RXD2 0 0 Figure 3-10. Port M I/O Register (PTM ...

Page 138

... SCI, or DAC1/0 function are disabled. Field 7:3, 1:0 Data Direction Port M DDRM[7:3, 0 Associated pin is configured as input. 1:0] 1 Associated pin is configured as output. 138 DDRM5 DDRM4 DDRM3 Table 3-9. DDRM Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. DDRM1 DDRM0 Freescale Semiconductor ...

Page 139

... This register configures the drive strength of configured output pins as either full or reduced pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Field 7:3, 1:0 Reduced Drive Port M RDRM[7:3, 0 Full drive strength at output 1:0] 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor RDRM5 RDRM4 RDRM3 Table 3-10 ...

Page 140

... A pull-up device is connected to the associated port M pin. 1: pull-down device is connected to the associated port M pin. 140 PERM5 PERM4 PERM3 Table 3-11. PERM Field Descriptions Description PPSM5 PPSM4 PPSM3 Table 3-12. PPSM Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. PERM1 PERM0 PPSM1 PPSM0 Freescale Semiconductor ...

Page 141

... If the IIC is enabled, the associated pins are always set to wired-or mode, and the state of the WOMM[7:6] bits have no effect. The WOMM[7:6] bits will not change to reflect their wired-or mode configuration when the IIC is enabled. Field 7:4 Wired-OR Mode Port M WOMM[7:4] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Freescale Semiconductor WOMM5 WOMM4 Table 3-13 ...

Page 142

... This register always reads back the status of the associated pins. 142 PTP5 PTP4 PTP3 PW05 PW04 PW03 Figure 3-17. Port P I/O Register (PTP PTIP5 PTIP4 PTIP3 Unaffected by reset Figure 3-18. Port P Input Register (PTIP) MC9S12E128 Data Sheet, Rev. 1. PTP2 PTP1 PTP0 PW02 PW01 PW00 PTIP2 PTIP1 PTIP0 Freescale Semiconductor ...

Page 143

... This register configures the drive strength of configured output pins as either full or reduced pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Field 5:0 Reduced Drive Port P RDRP[5:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor DDRP5 DDRP4 DDRP3 0 ...

Page 144

... A pull-up device is connected to the associated port P pin pull-down device is connected to the associated port P pin. 144 PERP5 PERP4 PERP3 Table 3-16. PERP Field Descriptions Description PPSP5 PPSP4 PPSP3 Table 3-17. PPSP Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. PERP2 PERP1 PERP0 PPSP2 PPSP1 PPSP0 Freescale Semiconductor ...

Page 145

... Port Q Input Register (PTIQ PTIQ6 W Reset Reserved or Unimplemented Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. Freescale Semiconductor PTQ5 PTQ4 PTQ3 IS1 IS0 FAULT3 Figure 3-23. Port Q I/O Register (PTQ) ...

Page 146

... Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 146 DDRQ5 DDRQ4 DDRQ3 Table 3-18. DDRQ Field Descriptions Description RDRQ5 RDRQ4 RDRQ3 Table 3-19. RDRQ Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. DDRQ2 DDRQ1 DDRQ0 RDRQ2 RDRQ1 RDRQ0 Freescale Semiconductor ...

Page 147

... The Port Q Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 6:0 Polarity Select Port Q PPSQ[6: pull-up device is connected to the associated port Q pin pull-down device is connected to the associated port Q pin. Freescale Semiconductor PERQ5 PERQ4 PERQ3 0 ...

Page 148

... This register always reads back the status of the associated pins. 148 PTS5 PTS4 PTS3 MOSI MISO TXD1 Figure 3-29. Port S I/O Register (PTS PTIS5 PTIS4 PTIS3 Unaffected by reset Figure 3-30. Port S Input Register (PTIS) MC9S12E128 Data Sheet, Rev. 1. PTS2 PTS1 PTS0 RXD1 TXD0 RXD0 PTIS2 PTIS1 PTIS0 Freescale Semiconductor ...

Page 149

... If the SPI, SCI1 and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Field 7:0 Data Direction Port S DDRS[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor DDRS5 DDRS4 DDRS3 0 ...

Page 150

... Pull Device Enable Port S PERS[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. 150 RDRS5 RDRS4 RDRS3 Table 3-23. RDRS Field Descriptions Description PERS5 PERS4 PERS3 Table 3-24. PERS Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. RDRS2 RDRS1 RDRS0 PERS2 PERS1 PERS0 Freescale Semiconductor ...

Page 151

... Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. Field 7:0 Wired-OR Mode Port S WOMS[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Freescale Semiconductor PPSS5 PPSS4 PPSS3 Table 3-25 ...

Page 152

... This register always reads back the status of the associated pins. 152 PTT5 PTT4 PTT3 OC15 OC14 OC07 Figure 3-36. Port T I/O Register (PTT PTIT5 PTIT4 PTIT3 Unaffected by reset Figure 3-37. Port T Input Register (PTIT) MC9S12E128 Data Sheet, Rev. 1. PTT2 PTT1 PTT0 OC06 OC05 OC04 PTIT2 PTIT1 PTIT0 Freescale Semiconductor ...

Page 153

... This register configures the drive strength of configured output pins as either full or reduced pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Field 7:0 Reduced Drive Port T RDRT[7:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor DDRT5 DDRT4 DDRT3 0 ...

Page 154

... A pull-up device is connected to the associated port T pin pull-down device is connected to the associated port T pin. 154 PERT5 PERT4 PERT3 Table 3-29. PERT Field Descriptions Description PPST5 PPST4 PPST3 Table 3-30. PPST Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. PERT2 PERT1 PERT0 PPST2 PPST1 PPST0 Freescale Semiconductor ...

Page 155

... Port U Input Register (PTIU PTIU7 PTIU6 W Reset Reserved or Unimplemented Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. Freescale Semiconductor PTU5 PTU4 PTU3 PW15 PW14 PW13 OC27 Figure 3-42. Port U I/O Register (PTU) ...

Page 156

... Field 7:0 Data Direction Port U DDRU[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. 156 DDRU5 DDRU4 DDRU3 Table 3-31. DDRT Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. DDRU2 DDRU1 DDRU0 Freescale Semiconductor ...

Page 157

... This register configures whether a pull- pull-down device is activated on configured input pins pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Field 7:0 Pull Device Enable Port U PERU[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Freescale Semiconductor RDRU5 RDRU4 RDRU3 0 ...

Page 158

... If enabled, TIM2 channel is connected to the associated port U pin enabled, PWM channel is connected to the associated port U pin. 158 PPSU5 PPSU4 PPSU3 Table 3-34. PPST Field Descriptions Description MODRR3 Table 3-35. MODRR Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. PPSU2 PPSU1 PPSU0 MODRR2 MODRR1 MODRR0 Freescale Semiconductor ...

Page 159

... Register bit set to 0 configures the pin as an input. A Data Direction Register bit set to 0 configures the pin as an output peripheral module controls the pin the contents of the data direction register is ignored (Figure 3-49). Freescale Semiconductor Chapter 3 Port Integration Module (PIM9E128V1) MC9S12E128 Data Sheet, Rev. 1.07 (Figure 3-49) ...

Page 160

... PTIx 0 1 PTx 0 1 DDRx 0 1 data out Digital Module output enable module enable 1 Digital Input 0 Module Enable Digital 0 Output Analog 1 Output PIM Boundary MC9S12E128 Data Sheet, Rev. 1.07 PAD 1 PAD Freescale Semiconductor ...

Page 161

... Applicable only on Port AD. 2 Digital outputs are disabled and digital input logic is forced to “1” when an analog module associated with the port is enabled. Freescale Semiconductor Table 3-36. Pin Configuration Summary Function X 0 Input 0 0 Input 1 0 Input 0 1 Input 1 1 Input ...

Page 162

... Disabled Hi-z Disabled Hi-z Disabled MC9S12E128 Data Sheet, Rev. 1.07 Section 3.3, “Memory Map and Table 3-37 summarizes the port Wired-OR Interrupt Mode N/A Disabled Disabled N/A Disabled N/A N/A N/A N/A N/A Disabled N/A N/A N/A N/A N/A Freescale Semiconductor ...

Page 163

... Figure 3-51. Interrupt Glitch Filter on Port AD (PPS = 0) Pulse Ignored Uncertain Valid 1 These values include the spread of the oscillator frequency over temperature, voltage and process. Freescale Semiconductor (Figure 3-52) shorter than a specified time from generating an t ifmin t ifmax Table 3-38. Pulse Detection Criteria ...

Page 164

... For other sources of external interrupts refer to the respective block description chapters. 164 t pulse Figure 3-52. Pulse Illustration Interrupt Local Flag Enable PIFAD[15:0] PIEAD[15:0] NOTE MC9S12E128 Data Sheet, Rev. 1.07 Global (CCR) Mask I Bit Freescale Semiconductor ...

Page 165

... System reset generation from the following possible sources: — Power-on reset — Low voltage reset Refer to the device overview section for availability of this feature. — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12E128 Data Sheet, Rev. 1.07 165 ...

Page 166

... Self-clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 4.1.3 Block Diagram Figure 4-1 shows a block diagram of the CRGV4. 166 MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 167

... PLL. Refer to the device overview chapter for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be tied DDPLL Freescale Semiconductor Power-on Reset 1 Low Voltage Reset CRG Reset ...

Page 168

... CTCTL is intended for factory test purposes only. 168 CS MCU RS XFC Figure 4-2. PLL Loop Filter Connections Table 4-1. CRGV4 Memory Map Use MC9S12E128 Data Sheet, Rev. 1.07 V DDPLL CP Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Freescale Semiconductor ...

Page 169

... REFDV CTFLG CRGFLG R RTIF W CRGINT R RTIE W CLKSEL R PLLSEL W PLLCTL R CME W RTICTL COPCTL R WCOP W FORBYP CTCTL Freescale Semiconductor NOTE SYN5 SYN4 REFDV3 PORF LVRF LOCKIF 0 0 LOCKIE PSTP SYSWAI ROAWAI PLLON AUTO ACQ RTR6 RTR5 RTR4 0 0 RSBCK Unimplemented or Reserved Figure 4-3. CRG Register Summary MC9S12E128 Data Sheet, Rev ...

Page 170

... Write to this register initializes the lock detector bit and the track detector bit. 170 Bit 6 Bit 5 Bit 4 = Unimplemented or Reserved SYNR = PLLCLK 2xOSCCLKx ---------------------------------- - REFDV NOTE SYN5 SYNR SYN3 NOTE MC9S12E128 Data Sheet, Rev. 1. Bit Bit 3 Bit 2 Bit 1 Bit 0 ). SCM SYN2 SYN1 0 0 Freescale Semiconductor 0 0 SYN0 0 ...

Page 171

... W Reset Unimplemented or Reserved Figure 4-6. CRG Reserved Register (CTFLG) Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes Writing to this register when in special mode can alter the CRGV4 functionality. Freescale Semiconductor Chapter 4 Clocks and Reset Generator (CRGV4 REFDV3 NOTE ...

Page 172

... Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode. TRACK Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status. 172 LOCK LVRF LOCKIF Note Figure 4-7. CRG Flag Register (CRGFLG) Table 4-2. CRGFLG Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1. TRACK SCM SCMIF Freescale Semiconductor ...

Page 173

... Interrupt will be requested whenever RTIF is set. 4 Lock Interrupt Enable Bit LOCKIE 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 Self-Clock Mode Interrupt Enable Bit SCMIE 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set. Freescale Semiconductor Description . SCM LOCKIE 0 ...

Page 174

... Core Stops in Wait Mode Bit — Write: anytime CWAI 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode. 174 Figure 4- SYSWAI ROAWAI PLLWAI Table 4-4. CLKSEL Field Descriptions Description MC9S12E128 Data Sheet, Rev. 1.07 for details on the effect of each bit CWAI RTIWAI COPWAI 0 0 Freescale Semiconductor 0 0 ...

Page 175

... Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. 4 Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect. ACQ 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. Freescale Semiconductor Description AUTO ...

Page 176

... Table 4-6. RTICTL Field Descriptions Description Table 4-7 shows all possible divide values selectable by the RTICTL register. The MC9S12E128 Data Sheet, Rev. 1.07 Section 4.5.1, “Clock Monitor Reset”). Section 4.4.7.2, “Self-Clock Mode”). RTR2 RTR1 RTR0 Table Freescale Semiconductor 4-7. ...

Page 177

... OFF* 1010 ( 11) OFF* 1011 ( 12) OFF* 1100 ( 13) OFF* 1101 ( 14) OFF* 1110 ( 15) OFF* 1111 ( 16) * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor Table 4-7. RTI Frequency Divide Rates RTR[6:4] = 001 010 011 ...

Page 178

... ARMCOP register) 178 Table 4-8. COPCTL Field Descriptions Description Table 4-9. COP Watchdog Rates OSCCLK CR1 CR0 Cycles to Time Out 0 0 COP disabled MC9S12E128 Data Sheet, Rev. 1. CR2 CR1 0 0 Table 4-9 Table 4-9). The COP Freescale Semiconductor 0 CR0 0 shows ...

Page 179

... Writing to this register when in special test modes can alter the CRG’s functionality Reset Unimplemented or Reserved Read: always read 0x0080 except in special modes Write: only in special modes Freescale Semiconductor NOTE Figure 4-13. Reserved Register (FORBYP) NOTE 5 ...

Page 180

... The PLL can change between acquisition and tracking modes either automatically or manually. 180 Bit 5 Bit 4 Bit Figure 4-15. ARMCOP Register Diagram SYNR PLLCLK 2 OSCCLK = ---------------------------------- - REFDV CAUTION MC9S12E128 Data Sheet, Rev. 1. Bit 2 Bit 1 Bit Freescale Semiconductor ...

Page 181

... The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor REFERENCE REFDV <3:0> ...

Page 182

... The following conditions apply when in sys MC9S12E128 Data Sheet, Rev. 1.07 , and is clear when trk , and is cleared Lock . ) before acq ) before selecting the PLLCLK al Freescale Semiconductor ...

Page 183

... PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum Freescale Semiconductor PLLSEL or SCM 1 ...

Page 184

... A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See 1. VCO clock cycles are generated by the PLL when running at minimum frequency f 184 1 is called check window. Figure 4-19 MC9S12E128 Data Sheet, Rev. 1. example. . SCM Freescale Semiconductor ...

Page 185

... Figure 4-20. Sequence for Clock Quality Check Remember that in parallel to additional actions caused by self-clock mode or clock monitor reset check the OSCCLK signal Clock Monitor Reset will always set the SCME bit to logical’1’ Freescale Semiconductor check window 4096 4095 osc ok Figure 4-19 ...

Page 186

... Reset).” The COP runs with a gated OSCCLK (see COP”). Three control bits in the COPCTL register allow selection MC9S12E128 Data Sheet, Rev. 1.07 ) and an active VREG CR[2:0] 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 COP TIMEOUT Section 4.5.2, Freescale Semiconductor ...

Page 187

... Self-Clock Mode The VCO has a minimum operating frequency failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO Freescale Semiconductor RTI”). At the end of the RTI time-out period the . WAIT(RTIWAI), RTI enable ...

Page 188

... MC9S12E128 Data Sheet, Rev. 1.07 Section 4.4.4, “Clock Quality COPWAI ROAWAI — — — — — — — — stopped — 1 — reduced Figure 4-23). Depending on Freescale Semiconductor ...

Page 189

... Core req’s Wait Mode. no PLLWAI=1 ? yes CWAI or Clear SYSWAI=1 PLLSEL, ? Disable PLL yes Disable core clocks Figure 4-23. Wait Mode Entry/Exit Sequence Freescale Semiconductor no no SYSWAI=1 ? yes Disable Enter system clocks Wait Mode Wait Mode left due to external reset Exit Wait w. ext.RESET no Exit Wait w ...

Page 190

... If wait mode is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 4-11 summarizes the outcome of a clock loss while in wait mode. 190 MC9S12E128 Data Sheet, Rev. 1.07 Section 4.4.4, “Clock Freescale Semiconductor ...

Page 191

... Continue to perform additional Clock Quality Checks until OSCCLK or an External RESET is applied. – Exit Wait Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK Freescale Semiconductor CRG Actions while in Wait Mode. is o.k. again. is o.k.again. ...

Page 192

... A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit. 192 CRG Actions ) as system clock, SCM MC9S12E128 Data Sheet, Rev. 1.07 Freescale Semiconductor ...

Page 193

... Wake-up from pseudo-stop is the same as wake-up from wait mode. There are also three different scenarios for the CRG to restart the MCU from pseudo-stop mode: • External reset • Clock monitor fail • Wake-up interrupt Freescale Semiconductor Core req’s Stop Mode. Clear PLLSEL, Disable PLL Wait Mode left Enter ...

Page 194

... MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 4-12 summarizes the outcome of a clock loss while in pseudo-stop mode. 194 MC9S12E128 Data Sheet, Rev. 1.07 Section 4.4.4, “Clock Freescale Semiconductor ...

Page 195

... External RESET is applied. – Exit Pseudo-Stop Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. Freescale Semiconductor Chapter 4 Clocks and Reset Generator (CRGV4) CRG Actions MC9S12E128 Data Sheet, Rev. 1. system clock ...

Page 196

... The reset values of registers and signals are provided in 196 CRG Actions SCM Checker”). After completing the clock quality check Checker”). If the clock quality check is successful, the NOTE Section 4.3, “Memory Map and Register MC9S12E128 Data Sheet, Rev. 1. system clock, Freescale Semiconductor ...

Page 197

... External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. Freescale Semiconductor Table 4-13. Refer to the device overview chapter for related Table 4-13 ...

Page 198

... CRG drives RESET pin low RESET pin released ) ( 128+n cycles 64 cycles with n being possibly min 3 / max 6 SYSCLK cycles depending not on internal running synchronization delay Figure 4-25. RESET Timing MC9S12E128 Data Sheet, Rev. 1. possibly RESET driven low externally Section 4.3, Freescale Semiconductor ...

Page 199

... Internal RESET Figure 4-26. RESET Pin Tied to V RESET Internal POR Internal RESET Figure 4-27. RESET Pin Held Low Externally Freescale Semiconductor Chapter 4 Clocks and Reset Generator (CRGV4) to the MCU has reached a certain level and asserts DD Clock Quality Check (no Self-Clock Mode) ...

Page 200

... Table Table 4-15. CRG Interrupt Vectors CCR Local Enable Mask I bit CRGINT (RTIE) I bit CRGINT (LOCKIE) I bit CRGINT (SCMIE) Section 4.4.4, “Clock Quality MC9S12E128 Data Sheet, Rev. 1.07 4-15. Refer to the device overview Checker.” If the clock monitor Freescale Semiconductor ...

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