MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 118

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
2.4.4
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash array memory according to
2.4.4.1
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/array being erased is not guaranteed.
2.4.5
The Flash module can generate an interrupt when all Flash commands have completed execution or the
Flash address, data, and command buffers are empty.
2.4.5.1
Figure 2-26
The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to
discriminate for the generation of interrupts.
For a detailed description of these register bits, refer to
(FCNFG)”
118
FPROT — Flash Protection Register (see
FSEC — Flash Security Register (see
Flash Address, Data, and Command
Buffers are empty
All Flash commands have completed
execution
and
Flash Reset Sequence
Interrupts
shows the logic used for generating interrupts.
Reset While Flash Command Active
Description of Interrupt Operation
Vector addresses and their relative interrupt priority are determined at the
MCU level.
Section 2.3.2.6, “Flash Status Register
Interrupt Source
CBEIE
CBEIF
CCIE
CCIF
Figure 2-26. Flash Interrupt Implementation
Table 2-17. Flash Interrupt Sources
MC9S12E128 Data Sheet, Rev. 1.07
Section
(FSTAT register)
(FSTAT register)
Interrupt Flag
NOTE
Section
CBEIF
CCIF
Table
2.3.2.2)
(FSTAT)”.
Section 2.3.2.4, “Flash Configuration Register
FLASH INTERRUPT REQUEST
2.3.2.5)
2-1:
Local Enable
CBEIE
CCIE
Global (CCR) Mask
Freescale Semiconductor
I Bit
I Bit

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