MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 149

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3.5.3
Read: Anytime. Write: Anytime.
This register configures port pins PS[7:4] and PS[2:0] as either input or output.
When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data
Direction Register bits have no effect.
When the SCI1 transmitter is enabled, the PS[3] pin becomes the TXD1 output pin and the associated Data
Direction Register bit has no effect. When the SCI1 receiver is enabled, the PS[2] pin becomes the RXD1
input pin and the associated Data Direction Register bit has no effect.
When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data
Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0
input pin and the associated Data Direction Register bit has no effect.
If the SPI, SCI1 and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
Freescale Semiconductor
DDRS[7:0]
Reset
Field
7:0
W
R
DDRS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port S Data Direction Register (DDRS)
0
7
DDRS6
0
6
Figure 3-31. Port S Data Direction Register (DDRS)
Table 3-22. DDRS Field Descriptions
DDRS5
MC9S12E128 Data Sheet, Rev. 1.07
0
5
DDRS4
0
4
Description
DDRS3
0
3
Chapter 3 Port Integration Module (PIM9E128V1)
DDRS2
0
2
DDRS1
0
1
DDRS0
0
0
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