MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 156

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3 Port Integration Module (PIM9E128V1)
3.3.7.3
Read: Anytime. Write: Anytime.
This register configures port pins PU[7:0] as either input or output.
If a pulse width modulator channel is enabled, the associated pin is forced to be an output and the
associated Data Direction Register bit has no effect. If the associated pulse width modulator channel is
disabled, the corresponding DDRUx bit reverts to control the I/O direction of the associated pin.
If the TIM2 module is enabled, each port pin configured for output compare is forced to be an output and
the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled,
the corresponding DDRUx bit reverts to control the I/O direction of the associated pin.
If the TIM2 module is enabled, each port pin configured as an input capture has the corresponding DDRUx
bit controlling the I/O direction of the associated pin.
When both a timer function and a PWM function are enabled on the same pin, the MODRR register
determines which function has control of the pin
156
DDRU[7:0]
Reset
Field
7:0
W
R
DDRU7
Data Direction Port U
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port U Data Direction Register (DDRU)
0
7
DDRU6
0
6
Figure 3-44. Port U Data Direction Register (DDRU)
Table 3-31. DDRT Field Descriptions
DDRU5
MC9S12E128 Data Sheet, Rev. 1.07
0
5
DDRU4
0
4
Description
DDRU3
0
3
DDRU2
0
2
DDRU1
Freescale Semiconductor
0
1
DDRU0
0
0