MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 183

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4.2
The clock generator creates the clocks used in the MCU (see
top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting
of the respective configuration bits.
The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The
memory blocks use the bus clock. If the MCU enters self-clock mode (see
Mode”), oscillator clock source is switched to PLLCLK running at its minimum frequency f
clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU.
The core clock is twice the bus clock as shown in
one bus clock.
PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned
off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
Freescale Semiconductor
EXTAL
XTAL
System Clocks Generator
OSCILLATOR
Condition
Gating
PHASE
LOCK
LOOP
= Clock Gate
OSCCLK
PLLCLK
Monitor
Clock
Figure 4-17. System Clocks Generator
PLLSEL or SCM
MC9S12E128 Data Sheet, Rev. 1.07
1
0
1
0
SCM
Figure
STOP(PSTP,PCE),
STOP(PSTP,PRE),
WAIT(COPWAI),
WAIT(SYSWAI),
WAIT(RTIWAI),
WAIT(SYSWAI),
STOP(PSTP)
COP enable
RTI enable
STOP
STOP
4-18. But note that a CPU cycle corresponds to
SYSCLK
Figure
Chapter 4 Clocks and Reset Generator (CRGV4)
4-17). The gating condition placed on
WAIT(CWAI,SYSWAI),
2
Section 4.4.7.2, “Self-Clock
STOP
CLOCK PHASE
GENERATOR
COP
RTI
SCM
Pseudo-Stop Mode
(running during
Core Clock
Bus Clock
. The bus
Oscillator
Oscillator
Clock
Clock
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