MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 259

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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8.4.1
This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow
pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer
specification defines a half-duplex infrared communication link for exchange data. The full standard
includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 kbits/s and
115.2 kbits/s.
The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The
SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse
for every 0 bit. No pulse is transmitted for every 1 bit. When receiving data, the IR pulses should be
detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external
from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit
stream to be received by the SCI. The polarity of transmitted pulses and expected receive pulses can be
inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low
pulses.
The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in
the infrared submodule in order to generate either 3/16, 1/16, or 1/32 narrow pulses during transmission.
The infrared block receives two clock sources from the SCI, R16XCLK, and R32XCLK, which are
configured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are
internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and
R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock.
8.4.1.1
The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A
narrow pulse is transmitted for a 0 bit and no pulse for a 1 bit. The narrow pulse is sent in the middle of
the bit with a duration of 1/32, 1/16, or 3/16 of a bit time.
8.4.1.2
The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is
expected for each 0 received and no pulse is expected for each 1 received. This receive decoder meets the
edge jitter requirement as defined by the IrDA serial infrared physical layer specification.
8.4.2
The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data
format where 0s are represented by light pulses and 1s remain low. See
Freescale Semiconductor
Infrared Interface Submodule
Data Format
Infrared Transmit Encoder
Infrared Receive Decoder
MC9S12E128 Data Sheet, Rev. 1.07
Chapter 8 Serial Communication Interface (SCIV3)
Figure
8-12.
259

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