MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 279

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.2
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
9.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when its configured as a master and its used as an input to receive the slave select
signal when the SPI is configured as slave.
9.2.4
This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of
slave.
9.3
This section provides a detailed description of address space and registers used by the SPI.
The memory map for the SPIV3 is given below in
of a base address and an address offset. The base address is defined at the SoC level and the address offset
is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
9.3.1
Freescale Semiconductor
1
2
3
Certain bits are non-writable.
Writes to this register are ignored.
Reading from this register returns all zeros.
Memory Map and Register Definition
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
MISO — Master In/Slave Out Pin
SCK — Serial Clock Pin
Module Memory Map
SS — Slave Select Pin
SPI Control Register 1 (SPICR1)
SPI Control Register 2 (SPICR2)
SPI Baud Rate Register (SPIBR)
SPI Status Register (SPISR)
Reserved
SPI Data Register (SPIDR)
Reserved
Reserved
MC9S12E128 Data Sheet, Rev. 1.07
Table 9-1. SPIV3 Memory Map
Table
Use
9-1. The address listed for each register is the sum
Chapter 9 Serial Peripheral Interface (SPIV3)
Access
R/W
R/W
—
—
—
R/W
R/W
R
2,3
2,3
2,3
2
1
1
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