MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 452

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 15 Background Debug Module (BDMV4)
15.3.2.1
Note:
1
2
Read: All modes through BDM operation
Write: All modes but subject to the following:
452
Special single-chip mode:
Special peripheral mode:
BDMACT
ENBDM is read as "1" by a debugging environment in Special single-chip mode when the device is not secured or secured
but fully erased (Flash and EEPROM).This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
UNSEC is read as "1" by a debugging environment in Special single-chip mode when the device is secured and fully erased,
else it is "0" and can only be read if not secure (see also bit description).
ENBDM
•
•
•
•
Field
7
6
BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the
standard BDM firmware lookup table upon exit from BDM active mode.
CLKSW can only be written via BDM hardware or standard BDM firmware write commands.
All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
ENBDM should only be set via a BDM hardware command if the BDM firmware commands are
needed. (This does not apply in special single-chip mode).
All other modes:
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode. In secure mode, this
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
0 BDM not active
1 BDM active
BDM Status Register (BDMSTS)
Reset:
bit will not be set by the firmware until after the EEPROM and FLASH erase verify tests are complete.
W
R
ENBDM
1
7
0
0
0
1
Figure 15-3. BDM Status Register (BDMSTS)
= Unimplemented or Reserved
Table 15-2. BDMSTS Field Descriptions
BDMACT
MC9S12E128 Data Sheet, Rev. 1.07
1
1
1
0
6
ENTAG
5
0
0
0
0
Description
SDV
0
0
0
0
4
TRACE
3
0
0
0
0
= Implemented (do not alter)
CLKSW
0
0
0
0
2
Freescale Semiconductor
UNSEC
0
1
0
0
0
2
0
0
0
0
0
0