MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 484

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 16 Debug Module (DBGV1)
16.3.2.4
484
Reset
Field
CNT
TBF
5:0
7
W
R
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was
last armed. If this bit is set, then all 64 words will be valid data, regardless of the value in CNT[5:0]. The TBF bit
is cleared when ARM in DBGC1 is written to a 1.
Count Value — The CNT bits indicate the number of valid data words stored in the trace buffer.
the correlation between the CNT bits and the number of valid data words in the trace buffer. When the CNT rolls
over to 0, the TBF bit will be set and incrementing of CNT will continue if DBG is in end-trigger mode. The
DBGCNT register is cleared when ARM in DBGC1 is written to a 1.
TBF
Debug Count Register (DBGCNT)
0
7
= Unimplemented or Reserved
0
0
6
TBF
Figure 16-8. Debug Count Register (DBGCNT)
0
0
0
0
1
1
Table 16-8. DBGCNT Field Descriptions
Table 16-9. CNT Decoding Table
MC9S12E128 Data Sheet, Rev. 1.07
0
5
000000
000001
000010
111110
111111
000000
000001
111111
CNT
..
..
..
..
0
4
64 words valid; if BEGIN = 1, the
oldest data has been overwritten
breakpoint will be generated if
Description
ARM bit will be cleared. A
by most recent data
64 words valid,
62 words valid
63 words valid
DBGBRK = 1
No data valid
2 words valid
Description
1 word valid
0
3
..
..
CNT
0
2
Freescale Semiconductor
0
1
Table 16-9
0
0
shows