MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 486

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 16 Debug Module (DBGV1)
16.3.2.6
486
PORTK/XAB
PPAGE
Reset
Reset
Field
7
15:0
SEE NOTE 1
PAGSEL
W
W
R
R
NOTES:
1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Bit 15
Bit 7
Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare
the address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode.
6
Debug Comparator C Register (DBGCC)
15
0
0
7
Figure 16-10. Comparator C Extended Comparison in BKP/DBG Mode
XAB21
PIX7
= Unimplemented or Reserved
= Unimplemented or Reserved
SEE NOTE 2
0
5
Figure 16-11. Debug Comparator C Register High (DBGCCH)
Figure 16-12. Debug Comparator C Register Low (DBGCCL)
Bit 14
Bit 6
14
0
0
6
XAB20
PIX6
0
4
Table 16-12. DBGCC Field Descriptions
XAB19
PIX5
Bit 13
Bit 5
MC9S12E128 Data Sheet, Rev. 1.07
3
13
0
0
5
DBGCXX
EXTCMP
XAB18
PIX4
2
Bit 12
Bit 4
12
0
0
4
XAB17
PIX3
1
Description
Table
XAB16
BIT 0
PIX2
Bit 11
Bit 3
11
16-13.
0
0
3
Table
XAB15
BIT 15
PIX1
16-11.
Bit 10
Bit 2
10
0
0
2
XAB14
BIT 14
PIX0
DBGCXH[15:12]
BIT 13
Freescale Semiconductor
Bit 9
Bit 1
0
0
9
1
BIT 12
Bit 8
Bit 0
0
0
8
0