MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 500

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 16 Debug Module (DBGV1)
16.4.2.6
The DBG in DBG mode can operate in four capture modes. These modes are described in the following
subsections.
16.4.2.6.1
In normal mode, the DBG module uses comparator A and B as triggering devices. Change-of-flow
information or data will be stored depending on TRG in DBGSC.
16.4.2.6.2
The intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information
from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the trace buffer, the DBG
module writes this value into the C comparator and the C comparator is placed in ignore address mode.
This will prevent duplicate address entries in the trace buffer resulting from repeated bit-conditional
branches. Comparator C will be cleared when the ARM bit is set in loop1 mode to prevent the previous
contents of the register from interfering with loop1 mode operation. Breakpoints based on comparator C
are disabled.
Loop1 mode only inhibits duplicate source address entries that would typically be stored in most tight
looping constructs. It will not inhibit repeated entries of destination addresses or vector addresses, because
repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is
designed to help find.
LOOP
LOOP2 BRN
500
INCX
BRCLR CMPTMP,#$0c,LOOP ; the BRCLR instruction also will be fetched by 1st P-cycle of BRCLR
NOP
DBNE
Capture Modes
*
A,LOOP2
Normal Mode
Loop1 Mode
In certain very tight loops, the source address will have already been fetched
again before the C comparator is updated. This results in the source address
being stored twice before further duplicate entries are suppressed. This
condition occurs with branch-on-bit instructions when the branch is fetched
by the first P-cycle of the branch or with loop-construct instructions in
which the branch is fetched with the first or second P cycle. See examples
below:
Loop1 mode does not support paged memory, and inhibits duplicate entries
in the trace buffer based solely on the CPU address. There is a remote
possibility of an erroneous address match if program flow alternates
between paged and unpaged memory space.
; 1-byte instruction fetched by 1st P-cycle of BRCLR
; 2-byte instruction fetched by 1st P-cycle of DBNE
; 1-byte instruction fetched by 2nd P-cycle of DBNE
; this instruction also fetched by 2nd P-cycle of DBNE
MC9S12E128 Data Sheet, Rev. 1.07
NOTE
NOTE
Freescale Semiconductor