MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 502

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 16 Debug Module (DBGV1)
the trigger is at the address of a change-of-flow address the trigger event will not be stored in the trace
buffer.
16.4.2.9
The data stored in the trace buffer can be read using either the background debug module (BDM) module
or the CPU provided the DBG module is enabled and not armed. The trace buffer data is read out first-in
first-out. By reading CNT in DBGCNT the number of valid words can be determined. CNT will not
decrement as data is read from DBGTBH:DBGTBL. The trace buffer data is read by reading
DBGTBH:DBGTBL with a 16-bit read. Each time DBGTBH:DBGTBL is read, a pointer in the DBG will
be incremented to allow reading of the next word.
Reading the trace buffer while the DBG module is armed will return invalid data and no shifting of the
RAM pointer will occur.
16.4.3
There are two ways of getting a breakpoint in DBG mode. One is based on the trigger condition of the
trigger mode using comparator A and/or B, and the other is using comparator C. External breakpoints
generated using the TAGHI and TAGLO external pins are disabled in DBG mode.
16.4.3.1
A breakpoint request to the CPU can be enabled by setting DBGBRK in DBGC1. The value of BEGIN in
DBGC1 determines when the breakpoint request to the CPU will occur. When BEGIN in DBGC1 is set,
begin-trigger is selected and the breakpoint request will not occur until the trace buffer is filled with
64 words. When BEGIN in DBGC1 is cleared, end-trigger is selected and the breakpoint request will occur
immediately at the trigger cycle.
There are two types of breakpoint requests supported by the DBG module, tagged and forced. Tagged
breakpoints are associated with opcode addresses and allow breaking just before a specific instruction
executes. Forced breakpoints are not associated with opcode addresses and allow breaking at the next
instruction boundary. The type of breakpoint based on comparators A and B is determined by TRGSEL in
the DBGC1 register (TRGSEL = 1 for tagged breakpoint, TRGSEL = 0 for forced breakpoint).
Table 16-26
502
Breakpoints
illustrates the type of breakpoint that will occur based on the debug run.
Reading Data from Trace Buffer
Breakpoint Based on Comparator A and B
The trace buffer should be read with the DBG module enabled and in the
same capture mode that the data was recorded. The contents of the trace
buffer counter register (DBGCNT) are resolved differently in detail mode
verses the other modes and may lead to incorrect interpretation of the trace
buffer data.
MC9S12E128 Data Sheet, Rev. 1.07
NOTE
Freescale Semiconductor