MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 550

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 19 Module Mapping Control (MMCV4)
19.3.2.4
Read: Anytime
Write: As stated in each bit description
This register initializes miscellaneous control functions.
550
1. The reset state of this bit is determined at the chip integration level.
EXSTR[1:0]
Reset: Special Test
ROMHM
ROMON
Reset: Expanded
Reset: Peripheral
Field
3:2
or Single Chip
1
0
or Emulation
External Access Stretch Bits 1 and 0
Write: once in normal and emulation modes and anytime in special modes
This two-bit field determines the amount of clock stretch on accesses to the external address space as shown in
Table
FLASH EEPROM or ROM Only in Second Half of Memory Map
Write: once in normal and emulation modes and anytime in special modes
0 The fixed page(s) of FLASH EEPROM or ROM in the lower half of the memory map can be accessed.
1 Disables direct access to the FLASH EEPROM or ROM in the lower half of the memory map. These physical
ROMON — Enable FLASH EEPROM or ROM
Write: once in normal and emulation modes and anytime in special modes
This bit is used to enable the FLASH EEPROM or ROM memory in the memory map.
0 Disables the FLASH EEPROM or ROM from the memory map.
1 Enables the FLASH EEPROM or ROM in the memory map.
Miscellaneous System Control Register (MISC)
locations of the FLASH EEPROM or ROM remain accessible through the program page window.
Writes to this register take one cycle to go into effect.
W
R
19-6. In single chip and peripheral modes these bits have no meaning or effect.
Stretch Bit EXSTR1
0
0
0
0
7
Figure 19-6. Miscellaneous System Control Register (MISC)
0
0
1
1
= Unimplemented or Reserved
Table 19-6. External Stretch Bit Definition
0
0
0
0
6
Table 19-5. INITEE Field Descriptions
MC9S12E128 Data Sheet, Rev. 1.07
Stretch Bit EXSTR0
0
0
0
0
5
0
1
0
1
NOTE
Description
0
0
0
0
4
Number of E Clocks Stretched
EXSTR1
1
1
1
3
0
1
2
3
EXSTR0
1
1
1
2
Freescale Semiconductor
ROMHM
0
0
0
1
ROMON
—
0
1
0
1