M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 182

IC M16C/28 MCU FLASH 96K 80LQFP

M30280FAHP#U5B

Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheets

Specifications of M30280FAHP#U5B

Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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M
R
R
1
e
E
. v
6
J
Figure 13.23 Phase-delayed Waveform Output Mode
0
C
2
9
2 /
0 .
B
8
0
0
0
G
4
J
(1) Free-running operation
(2) Base timer is reset when the base timer matches either following register
7
a
o r
0 -
. n
u
(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to "0")
(a) G1PO0 (enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or
(b) G1BTRR (enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
2
p
3
0
The above applies under the following conditions.
The above applies under the following conditions.
, 1
Base timer
G1IRj bit
Base timer
OUTC1j pin
G1IRj bit
OUTC1j pin
0
(
M
2
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value). The INV bit
is set to "0" (not inversed).
The UD1 to UD0 bits are set to "00
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value).
The INV bit is set to "0" (not inversed).
The UD1 to UD0 bits are set to "00
1
0
0
6
7
C
2 /
page 160
, 8
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
j=1 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
M
FFFF
0000
FFFF
0000
1
6
n+2
C
16
16
16
m
m
16
2 /
f o
8
3
) B
8
5
f
m
BT1
2
2
" (counter increment mode).
" (counter increment mode).
Inverse
Inverse
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
n+2
f
BT1
65536
f
BT1
n: Setting value of either register G1PO0 or G1BTRR
Inverse
65536X2
n+2
f
BT1
Inverse
f
BT1
65536
f
BT1
Inverse
13. Timer S

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