M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 211

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Figure 14.20 T
. v
6
J
0
C
2
9
Figure 14.19 Serial Data Logic Switching
2 /
0 .
B
14.1.2.5 TxD and RxD I/O Polarity Inverse Function (UART2)
8
0
0
This function inverses the polarities of the T
input/output data (including the start, stop and parity bits) are inversed. Figure 14.20 shows the T
pin output and R
0
G
4
14.1.2.4 Serial Data Logic Switching Function (UART2)
J
7
a
o r
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial
data logic.
0 -
. n
u
NOTES:
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
(2) When the U2LCH bit in the U2C1 register is set "1" (reverse)
2
(1) When the IOPOL bit in the U2MR register is set to "0" (no reverse)
(2) When the IOPOL bit in the U2MR register is set to "1" (reverse)
p
Transfer clock
3
Transfer clock
NOTES:
0
, 1
Transfer clock
Transfer clock
0
(
1. This applies to the case where the CKPOL bit in the U2C0 register
M
(no reverse)
2
1. This applies to the case where the UFORM bit in the U2C0 register
X
(no reverse)
(no reverse)
1
0
is set to "0" (transmit data output at the falling edge of the transfer
clock), the UFORM bit in the U2C0 register is set to "0" (LSB first),
the STPS bit in the U2MR register is set to "0" (1 stop bit) and the
PRYE bit in the U2MR register is set to "1" (parity enabled).
(reverse)
D and R
0
6
(reverse)
(reverse)
is set to "0"(LSB first), the STPS bit in the U2MR register is set to "0
" (1 stop bit) and the PRYE bit in the U2MR register is set to "1"(
parity enabled).
7
C
TxD
TxD
RxD
TxD
RxD
TxD
2 /
, 8
2
page 189
2
X
2
2
2
2
D pin input polarity inverse.
M
“H”
“L”
“H”
X
“L”
“H”
“L”
“H”
“H”
“H”
“H”
“L”
“H”
“H”
“H”
“L”
“L”
“L”
“L”
“L”
“L”
D I/O Polarity Inverse
1
6
C
2 /
f o
8
3
) B
8
ST
ST
ST
ST
ST
5
ST
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D1
D1
X
D2 pin output and R
D2
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
D3
D4
D4
D4
D4
D4
D4
D5
D5
D5
D5
D5
D5
X
D6
D6
D6
D6
D6
D6
D2 pin input. The logic levels of all
D7
D7
D7
D7
D7
D7
P
P
P
P
P
P
ST : Start bit
P : Parity bit
SP : Stop bit
SP
SP
SP
SP
SP
SP
ST : Start bit
P : Parity bit
SP : Stop bit
14. Serial I/O
X
D