M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 389

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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20.8 Serial I/O
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20.8.1 Clock-Synchronous Serial I/O
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20.8.1.1 Transmission/reception
20.8.1.2 Transmission
20.8.1.3 Reception
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1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin
2. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
register is set to “0” (transmit data output at the falling edge and the receive data taken in at the rising
edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register
is set to “1” (transmit data output at the rising edge and the receive data taken in at the falling edge of
the transfer clock), the external clock is in the low state.
1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix
2. When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to "1" (transmission
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every
5. When an external clock is selected, make sure the external clock is in high state if the CKPOL bit is
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goes to “L” when the data-receivable status becomes ready, which informs the transmission side
that the reception has become ready. The output level of the RTSi pin goes to “H” when reception
starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can
transmission and reception data with consistent timing. With the internal clock, the RTS function
has no effect.
(three-phase output forcible cutoff by input on SD pin enabled), the P7
U1MAP bit in PACR register is “1”) and CLK
• The TE bit in UiC1 register is set to “1” (transmission enabled)
• The TI bit in UiC1 register is set to “0” (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin is set to “L”
settings for transmission even when using the device only for reception. Dummy data is output to
the outside from the TxDi pin when receiving data.
enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated.
When an external clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to "1" and write dummy
data to the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi
input pin.
receive register while the RE bit in the UiC1 register (i = 0 to 2) is set to “1” (data present in the UiRB
register), an overrun error occurs and the UiRB register OER bit is set to “1” (overrun error oc-
curred). In this case, because the content of the UiRB register is indeterminate, a corrective mea-
sure must be taken by programs on the transmit and receive sides so that the valid data before the
overrun error occurred will be retransmitted. Note that when an overrun error occurred, the SiRIC
register IR bit does not change state.
time reception is made.
set to “0”, and in low state if the CKPOL bit is set to “1” before the following conditions are met:
• The RE bit in the UiC1 register is set to “1” (reception enabled)
• The TE bit in the UiC1 register is set to “1” (transmission enabled)
• The TI bit in the UiC1 register= “0” (data present in the UiTB register)
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pins go to a high-impedance state.
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20. Precautions
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