MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet
MC9S12NE64VTU
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MC9S12NE64 Data Sheet HCS12 Microcontrollers MC9S12NE64V1 Rev. 1.1 06/2006 freescale.com ...
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MC9S12NE64 Data Sheet MC9S12NE64V1 Rev. 1.1 06/2006 ...
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... Fixed labels for addresses $0167-$0169 on Detailed Register map. June 27, 2006 1.1 Updated PHY Rx and Tx ESD protection characteristics on Table A-3. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. 4 Description MC9S12NE64 Data Sheet, Rev ...
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... Penta Output Voltage Regulator (VREGPHYV1 379 Chapter 14 Interrupt (INTV1 387 Chapter 15 Multiplexed External Bus Interface (MEBIV3 395 Chapter 16 Module Mapping Control (MMCV4 423 Chapter 17 Background Debug Module (BDMV4 443 Chapter 18 Debug Module (DBGV1 469 Freescale Semiconductor LIST OF CHAPTERS MC9S12NE64 Data Sheet, Rev. 1.1 5 ...
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... MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Kbyte Flash Module (S12FTS64KV3) 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Freescale Semiconductor TABLE OF CONTENTS Chapter 1 MC9S12NE64 Device Overview , V SS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Chapter 2 MC9S12NE64 Data Sheet, Rev. 1.1 7 ...
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... Port and BKGD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.4.13 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.4.14 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.6.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.6.2 Recovery from Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8 Chapter 3 MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... EXTAL and XTAL — Clock/Crystal Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.2.3 XCLKS — Colpitts/Pierce Oscillator Selection Signal . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Freescale Semiconductor Chapter 4 — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 143 Chapter 5 Oscillator (OSCV2) — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 178 MC9S12NE64 Data Sheet, Rev ...
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... ETRIG3, ETRIG2, ETRIG1, and ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . 206 7.2 — High and Low Reference Voltage Pins . . . . . . . . . . . . . . . . . . . . . . . . 206 RH and RL 7.2.4 V and V DDA SSA 7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 10 Chapter 6 Timer Module (TIM16B4CV1) Chapter 7 — Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 9.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 9.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 9.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 9.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Freescale Semiconductor Chapter 8 Chapter 9 MC9S12NE64 Data Sheet, Rev. 1.1 11 ...
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... Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 10.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 10.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 12 Chapter 10 Inter-Integrated Circuit (IICV2) MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... PHY_TXN — EPHY Twisted Pair Output – 349 12.2.3 PHY_RXP — EPHY Twisted Pair Input + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.2.4 PHY_RXN — EPHY Twisted Pair Input – 350 12.2.5 PHY_RBIAS — EPHY Bias Control Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Freescale Semiconductor Chapter 11 Chapter 12 MC9S12NE64 Data Sheet, Rev. 1.1 ...
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... POR - Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.4.4 LVR - Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.4.5 CTRL - Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 13.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 14 Chapter 13 MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Freescale Semiconductor Chapter 14 Interrupt (INTV1) Chapter 15 Chapter 16 MC9S12NE64 Data Sheet, Rev. 1.1 ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 18.4.1 DBG Operating in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 16 Chapter 17 Chapter 18 Debug Module (DBGV1) MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... A.16 SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 A.16.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 A.16.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 A.17 Voltage Regulator Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 A.17.1 MCU Power-Up and LVR Graphical Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 A.17.2 Output Loads 540 Freescale Semiconductor Appendix A Electrical Characteristics MC9S12NE64 Data Sheet, Rev. 1.1 17 ...
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... B.1.5 EPHY LED Indicator Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 B.2 PCB Design Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 B.2.1 General PCB Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 B.2.2 Ethernet PCB Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 C.1 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 C.2 80-Pin TQFP-EP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 18 Appendix B Appendix C Package Information MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
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... port bits available for wakeup interrupt function with digital filtering • Memory — 64K bytes of FLASH EEPROM — 8K bytes of RAM • Analog-to-digital converter (ATD) — One 8-channel module with 10-bit resolution — External conversion trigger capability Freescale Semiconductor MC9S12NE64 Data Sheet, Rev 1.0 19 ...
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... Auto-negotiation next page ability — Baseline wander (BLW) correction — 125-MHz clock generator and timing recovery — Integrated wave-shaping circuitry — Loopback modes • CRG (clock and reset generator module) — Windowed COP watchdog — Real-time interrupt 20 MC9S12NE64 Data Sheet, Rev 1.0 Freescale Semiconductor ...
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... MHz. If using MEBI from 2.5 MHz to 16 MHz, only 10BASE-T communication is available. 2.No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying the FLASH difficult for unauthorized users. ...
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... PG5 KWG5 KWG6 PG6 KWG7 PG7 KWH0 PH0 KWH1 PH1 KWH2 PH2 KWH3 PH3 KWH4 PH4 PH5 KWH5 KWH6 PH6 PL0 ACTLED PL1 LNKLED PL2 SPDLED PL3 DUPLED COLLED PL4 PL5 PL6 PHY_RBIAS PHY_VSSA PHY_VDDA PHY_VSSRX PHY_VDDRX PHY_VSSTX PHY_VDDTX Freescale Semiconductor ...
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... Information about the HCS12 core can be found in the MMC, INT, MEBI, BDM, and DBG block description chapters in this data sheet, and also in the HCS12 CPU Reference Manual, S12CPUV2/D. Freescale Semiconductor Table 1-1. Device Register Map Overview 1 Module CORE (Ports Modes, Inits — MMC, INT, ...
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... MC9S12NE64 Data Sheet, Rev 1.0 1K REGISTER SPACE MAPPABLE TO ANY 2K BOUNDARY 8K BYTES RAM MAPPABLE TO ANY 8K BOUNDARY 0.5K, 1K, 2K PROTECTED SECTOR 16K FIXED FLASH EEPROM 16K PAGE WINDOW FOUR * 16K FLASH EEPROM PAGES 16K FIXED FLASH EEPROM 2K, 4K, 8K, OR 16K PROTECTED BOOT SECTOR BDM (IF ACTIVE) Freescale Semiconductor ...
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... Write: $0010 - $0014 Module Mapping Control Module (MMC) Map Address Name Read: $0010 INITRM Write: Read: $0011 INITRG Write: Read: $0012 INITEE Write: Read: $0013 MISC Write: Read: $0014 MTST0 Write: Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Bit ...
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... INT4 INT2 INT0 Bit 3 Bit 2 Bit 1 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 ID11 ID10 ID9 ID8 ID3 ID2 ID1 ID0 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM_SW2 RAM_SW1 RAM_SW0 0 0 PAG_SW1 PAG_SW0 Bit 3 Bit 2 Bit 1 Bit Freescale Semiconductor ...
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... Write: DBGCBH Read: $002E 1 (BKP1H) Write: DBGCBL Read: $002F 1 (BKP1L) Write: 1 Legacy HCS12 MCUs used this name for this register. Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit 4 PSEL7 PSEL6 PSEL5 PSEL4 Bit 7 Bit 6 Bit 5 Bit 4 DBGEN ARM TRGSEL BEGIN AF BF ...
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... Bit 3 Bit 2 Bit 1 Bit Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 SYN3 SYN2 SYN1 SYN0 REFDV3 REFDV2 REFDV1 REFDV0 LOCK TRACK SCM SCMIF SCMIE PLLWAI CWAI RTIWAI COPWAI 0 PRE PCE SCME RTR3 RTR2 RTR1 RTR0 0 CR2 CR1 CR0 Bit 0 Freescale Semiconductor ...
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... Write: Read: $0058 TC4 (hi) Write: Read: $0059 TC4 (lo) Write: Read: $005A TC5 (hi) Write: Read: $005B TC5 (lo) Write: Read: $005C TC6 (hi) Write: Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit 4 IOS7 IOS6 IOS5 IOS4 FOC7 FOC6 FOC5 FOC4 OC7M7 OC7M6 OC7M5 OC7M4 OC7D7 ...
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... PAOVI PAI 0 0 PAOVF PAIF Bit Bit Bit 3 Bit 2 Bit 1 Bit 0 0 WRAP2 WRAP1 WRAP0 0 ETRIG ETRIG ETRIG CH2 CH1 CH0 ASCIF ETRIGE ASCIE S1C FIFO FRZ1 FRZ0 PRS3 PRS2 PRS1 PRS0 CC2 CC1 CC0 CCF3 CCF2 CCF1 CCF0 Freescale Semiconductor ...
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... Write: Read: $009C ATDDR6H Write: Read: $009D ATDDR6L Write: Read: $009E ATDDR7H Write: Read: $009F ATDDR7L Write: $00A0 - $00C7 Reserved Read: $00A0 Reserved – $00C7 Write: Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit IEN7 IEN6 IEN5 IEN4 PTAD6 PTAD5 PTAD4 Bit15 14 13 ...
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... MC9S12NE64 Data Sheet, Rev 1.0 Bit 3 Bit 2 Bit 1 Bit 0 SBR11 SBR10 SBR9 SBR8 SBR3 SBR2 SBR1 SBR0 WAKE ILT RWU SBK RAF BRK13 TXDIR Bit 3 Bit 2 Bit 1 Bit 0 SBR11 SBR10 SBR9 SBR8 SBR3 SBR2 SBR1 SBR0 WAKE ILT RWU SBK RAF BRK13 TXDIR Freescale Semiconductor ...
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... IBSR Write: Read: $00E4 IBDR Write: Read: $00E5 – Reserved $00E7 Write: $00E8 - $00FF Reserved Address Name Read: $00E8- Reserved $00FF Write: Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit 4 SPIE SPE SPTIE MSTR MODFEN BIDIROE 0 SPPR2 SPPR1 SPPR0 SPIF 0 SPTEF MODF ...
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... MC9S12NE64 Data Sheet, Rev 1.0 Bit 3 Bit 2 Bit 1 Bit 0 FDIV3 FDIV2 FDIV1 FDIV0 NV3 NV2 SEC1 SEC0 FPHS0 FPLDIS FPLS1 FPLS0 0 BLANK CMDB2 CMDB0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 0 LEDEN EPHYWAI EPHYIEN EPHYIF Bit 3 Bit 2 Bit 1 Bit Freescale Semiconductor ...
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... Reserved Write: Read: $0150 MPADR Write: Read: $0151 MRADR Write: Read: $0152 MWDATA Write: Read: $0123 MWDATA Write: Read: $0154 MRDATA Write: Read: $0155 MRDATA Write: Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit EMACE ESWAI RFCE 0 CSLF PTRC 0 0 FPET FEMW ...
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... Write: 36 Bit 7 Bit 6 Bit 5 Bit BUSY NOPRE BUFMAP MAXFL[7: RXAEFP[7: RXBEFP[7: TXEFP[7:0] MCHASH[63:56] MCHASH[55:48] MCHASH[47:40] MCHASH[39:32] MCHASH[31:24] MCHASH[23:16] MCHASH[15:8] MCHASH[7:0] MACAD[47:40] MACAD[39:32] MACAD[31:24] MACAD[23:16] MACAD[15:8] MC9S12NE64 Data Sheet, Rev 1.0 Bit 3 Bit 2 Bit 1 Bit 0 MDCSEL MAXFL[10:8] 0 RXAEFP[10:8] 0 RXBEFP[10:8] 0 TXEFP[10:8] Freescale Semiconductor ...
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... PTS Write: Read: $0249 PTIS Write: Read: $024A DDRS Write: Read: $024B RDRS Write: Read: $024C PERS Write: Read: $024D PPSS Write: Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit 4 MACAD[7:0] 0 INDEX MISC[7:0] Bit 7 Bit 6 Bit 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 PTT7 PTT6 ...
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... RDRH2 RDRH1 RDRH0 PERH3 PERH2 PERH1 PERH0 PPSH3 PPSH2 PPSH1 PPSH0 PIEH3 PIEH2 PIEH1 PIEH0 PIFH3 PIFH2 PIFH1 PIFH0 PTJ3 PTJ2 PTJ1 PTJ0 PTIJ3 PTIJ2 PTIJ1 PTIJ0 DDRJ3 DDRJ2 DDRJ1 DDRJ0 RDRJ3 RDRJ2 RDRJ1 RDRJ0 PERJ3 PERJ2 PERJ1 PERJ0 Freescale Semiconductor ...
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... MC9S12NE64 1 The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor (or non full) mask set revision Freescale Semiconductor Bit 7 Bit 6 Bit 5 Bit ...
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... This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 40 shows the read-only values of these registers. See the module mapping Table 1-3. Memory Size Registers Register Name MEMSIZ0 MEMSIZ1 MC9S12NE64 Data Sheet, Rev 1.0 Value $03 $80 Freescale Semiconductor ...
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... Signals shown in Bold are not available on the 80-pin package MII_COL/KWJ3/PJ3 21 MII_RXD0/KWG0/PG0 22 MII_RXD1/KWG1/PG1 23 MII_RXD2/KWG2/PG2 24 MII_RXD3/KWG3/PG3 25 MII_RXCLK/KWG4/PG4 26 MII_RXDV/KWG5/PG5 27 MII_RXER/KWG6/PG6 28 Figure 1-3. Pin Assignments in 112-Pin LQFP for MC9S12NE64 Freescale Semiconductor 112-PIN LQFP MC9S12NE64 Data Sheet, Rev 1.0 Signal Description Figure 1-3 and 84 PL0/ACTLED 83 PL1/LNKLED 82 VDDR 81 PL2/SPDLED 80 PA7/ADDR15/DATA15 79 PA6/ADDR14/DATA14 ...
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... MII_RXDV/KWG5/PG5 MII_RXER/KWG6/PG6 Figure 1-4. Pin Assignments in 80-Pin TQFP-EP for MC9S12NE64 42 Recommendations.” 80-PIN TPFP- MC9S12NE64 Data Sheet, Rev 1.0 60 PL0/ACTLED 59 PL1/LNKLED 58 VDDR 57 PL2/SPDLED 56 PHY_VSSRX 55 PHY_VDDRX 54 PHY_RXN 53 PHY_RXP 52 PHY_VSSTX 51 PHY_TXN 50 PHY_TXP 49 PHY_VDDTX 48 PHY_VDDA 47 PHY_VSSA 46 PHY_RBIAS 45 VDD2 44 VSS2 43 PL3/DUPLED 42 PL4/COLLED 41 BKGD/MODC Freescale Semiconductor ...
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... PB[7:0] 16– VDDX1 VSSX1 PJ2 PJ3 PG0 PG1 Freescale Semiconductor Table 1-4. Signal Properties (Sheet Pin Pin Name Name Function Function Domain KWH6 MII_TXER KWH5 MII_TXEN KWH4 MII_TXCLK KWH3 MII_TXD3 KWH2 MII_TXD2 KWH1 MII_TXD1 KWH0 MII_TXD0 KWJ0 MII_MDC KWJ1 ...
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... Port E I/O pin; pipe While RESET VDDX status; mode pin is low: Down selection Port E I/O pin; bus VDDX PUCR Up clock output See Table 1-5 See Table 1-5 Freescale Semiconductor Reset State Input Input Input Input Input Input Input Input Input Input Input Input ...
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... PA[7:0] 77– VSS2 VDD2 PHY_RBIAS PHY_VSSA PHY_VDDA PHY_VDDTX PHY_TXP Freescale Semiconductor Table 1-4. Signal Properties (Sheet Pin Pin Name Name Function Function Domain — — — — — — VDDPLL — — — — VDDPLL — — VDDPLL — — — ...
Page 46
... TIM input cap. PPST output compare PERJ/ Port J I/O pin; IIC VDDX Disabled PPSJ SCL; interrupt PERJ/ Port J I/O pin; IIC VDDX Disabled PPSJ SDA; interrupt Freescale Semiconductor Reset State Analog Output Analog Input Analog Input Input Input Input Input Input Input ...
Page 47
... PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins PA[7:0] are general-purpose I/O pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:0] pins are not available in the 80-pin package version. Freescale Semiconductor NOTE NOTE A.12.3.1, “ ...
Page 48
... See the MISC register (EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the ECLK is available for use in external select decode logic constant speed clock for use in the external application system. 48 MC9S12NE64 Data Sheet, Rev 1.0 Freescale Semiconductor ...
Page 49
... RESET, the state of the PK7 pin is latched to the ROMON bit. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPKE in the PUCR register. PK7 is not available in the 80-pin package version. Freescale Semiconductor MC9S12NE64 Data Sheet, Rev 1.0 Signal Description ...
Page 50
... MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG5 pin is configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin configurations. 50 MC9S12NE64 Data Sheet, Rev 1.0 Freescale Semiconductor ...
Page 51
... While in reset and immediately out of reset, the PH6 pin is configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin configurations. Freescale Semiconductor MC9S12NE64 Data Sheet, Rev 1.0 Signal Description ...
Page 52
... While in reset and immediately out of reset, the PH0 pin is configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin configurations. 52 MC9S12NE64 Data Sheet, Rev 1.0 Freescale Semiconductor ...
Page 53
... MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ0 pin is configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EMAC block description chapter for information about pin configurations. Freescale Semiconductor MC9S12NE64 Data Sheet, Rev 1.0 Signal Description ...
Page 54
... PL1 pin is configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for information about pin configurations. 54 MC9S12NE64 Data Sheet, Rev 1.0 Freescale Semiconductor ...
Page 55
... PS3 becomes the transmit pin, TXD, of SCI1. While in reset and immediately out of reset, the PS3 pin is configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SCI block description chapter for information about pin configurations. Freescale Semiconductor MC9S12NE64 Data Sheet, Rev 1.0 Signal Description ...
Page 56
... PHY_RXP — EPHY Twisted Pair Input + Ethernet twisted pair input pin. This pin is hi-z out of reset. 1.2.3.59 PHY_RXN — EPHY Twisted Pair Input – Ethernet twisted pair input pin. This pin is hi-z out of reset. 56 MC9S12NE64 Data Sheet, Rev 1.0 Freescale Semiconductor ...
Page 57
... External power is supplied to the Ethernet physical transceiver (EPHY) transmitter through PHY_VDDTX and PHY_VSSTX. This 2.5 V supply is derived from the internal voltage regulator. No static load is allowed on these pins. The internal voltage regulator is turned off Freescale Semiconductor , V — Power & Ground Pins for I/O & Internal ...
Page 58
... Provide operating voltage and ground for the phase-locked loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. NOTE MC9S12NE64 Data Sheet, Rev 1 tied to ground. DDR REGEN REGEN SSX /V voltages and DD SS Freescale Semiconductor ...
Page 59
... ROMON bit in the MISC register thus controlling whether the internal FLASH is visible in the memory map. ROMON = 1 means the FLASH is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the RESET signal. Freescale Semiconductor core clock bus clock oscillator clock Figure 1-5 ...
Page 60
... The security byte resides in a portion of the FLASH array. See the FLASH block description chapter for more details on the security configuration. 1.No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying the FLASH difficult for unauthorized users. ...
Page 61
... Other peripherals are turned off. This mode consumes more current than the full stop mode, but the wakeup time from this mode is significantly shorter. Freescale Semiconductor MC9S12NE64 Data Sheet, Rev 1.0 Low-Power Modes ...
Page 62
... Local Enable to Elevate None COPCTL (CME, FCME) COP rate select None None None I-Bit INTCR (IRQEN) I-Bit CRGINT (RTIE) I-Bit T0IE (T0C4I) I-Bit T0IE (T0C5I) I-Bit T0IE (T0C6I) I-Bit T0IE (T0C7I) Freescale Semiconductor — — — — — — $F2 $F0 $E6 $E4 $E2 $E0 ...
Page 63
... Vemacrxbbo 45 $FFA4, $FFA5 Vemacbrxerr 46 $FFA2, $FFA3 Vemaclc 47 $FFA0, $FFA1 Vemacec 48 through $FF80 to $FF9F 63 Freescale Semiconductor CCR Interrupt Source Mask Standard timer overflow I-Bit Pulse accumulator overflow I-Bit Pulse accumulator input edge I-Bit SPI I-Bit SCI0 I-Bit SCI1 ...
Page 64
... PHY_VDDRX, PHY_VDDTX, and DD1 DD2 DDPLL , V SS2 and V SS1 SS2 MC9S12NE64 Data Sheet, Rev 1.0 Vector $FFFE, $FFFF $FFFE, $FFFF $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB and and V /V DD1 SS1 DD2 are connected together internally. This Freescale Semiconductor of the ). SS2 ...
Page 65
... Transmit and receive operations are not possible in wait mode if the CWAI bit is set in the CLKSEL register because the clocks to the transmit and receive buffers are stopped recommended that the EMAC ESWAI bit be set if wait mode is entered with the CWAI set. Freescale Semiconductor 1.7.6, “Ethernet Physical Transceiver MC9S12NE64 Data Sheet, Rev 1.0 Block Confi ...
Page 66
... CPU and the EMAC. No hardware blocking mechanism is implemented to prevent the CPU from accessing the Ethernet RAM space, so care must be taken to ensure that the CPU does not corrupt the RAM Ethernet contents. 66 MC9S12NE64 Data Sheet, Rev 1.0 Freescale Semiconductor ...
Page 67
... Security feature to prevent unauthorized access to the Flash memory • Code integrity check using built-in data compression 2.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Freescale Semiconductor CAUTION MC9S12NE64 Data Sheet, Rev. 1.1 Section 2.4.1 for details). 67 ...
Page 68
... Interface Command Pipeline comm1 comm2 addr1 addr2 data1 data2 Protection Security FCLK Figure 2-1. FTS64K Block Diagram Figure 2-2. The HCS12 architecture places the Flash memory MC9S12NE64 Data Sheet, Rev. 1.1 Flash Block 32K * 16 Bits sector 0 sector 1 sector 127 Freescale Semiconductor ...
Page 69
... Security information that allows the MCU to restrict access to the Flash module is stored in the Flash configuration field, described in Unpaged Flash Address 0xFF00 - 0xFF07 0xFF08 - 0xFF0C 0xFF0D 0xFF0E 0xFF0F Freescale Semiconductor Section 2.3.2.5, “Flash Protection Register Table 2-1. Table 2-1. Flash Configuration Field Paged Flash Address Size (PPAGE 0x3F) (bytes) ...
Page 70
... Kbytes 0x3E 0x5000 0x8000 16K PAGED Flash Block MEMORY 0x3C 0x3D 0xC000 Flash Protected High Sectors 0x3F 0xE000 Kbytes 0xF000 0xF800 0xFF00 - 0xFF0F, Flash Configuration Field Figure 2-2. Flash Memory Map MC9S12NE64 Data Sheet, Rev. 1.1 0x3E 0x3F Freescale Semiconductor ...
Page 71
... Flash Status Register (FSTAT) 0x0006 Flash Command Register (FCMD) 0x0007 Flash Control Register (FCTL) 0x0008 Flash High Address Register (FADDRHI) 0x0009 Flash Low Address Register (FADDRLO) Freescale Semiconductor Protectable Lower Protectable Range Higher Range 0x4000-0x41FF N.A. 0x4000-0x43FF 0x4000-0x47FF 0x4000-0x4FFF N.A. ...
Page 72
... Chapter 2 64 Kbyte Flash Module (S12FTS64KV3) 0x000A Flash High Data Register (FDATAHI) 0x000B Flash Low Data Register (FDATALO) 0x000C RESERVED2 0x000D RESERVED3 0x000E RESERVED4 0x000F RESERVED5 1 Intended for factory test purposes only. 72 Table 2-3. Flash Register Map MC9S12NE64 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 73
... R FPOPEN W FSTAT R CBEIF W FCMD FCTL R NV7 W FADDRHI FADDRLO R W FDATAHI R W FDATALO R W RESERVED1 Freescale Semiconductor PRDIV8 FDIV5 FDIV4 RNV5 RNV4 CCIE KEYACC RNV6 FPHDIS FPHS CCIF PVIOL ACCERR NV6 NV5 NV4 FADDRHI FADDRLO FDATAHI FDATALO Unimplemented or Reserved Figure 2-3. FTS64K Register Summary MC9S12NE64 Data Sheet, Rev. 1.1 Memory Map and Register Defi ...
Page 74
... The FSEC register holds all bits associated with the security of the MCU and Flash module Unimplemented or Reserved FDIV5 FDIV4 FDIV3 Table 2-4. FCLKDIV Field Descriptions Description . . MC9S12NE64 Data Sheet, Rev. 1 Bit FDIV2 FDIV1 FDIV0 0 0 Section 2.4.1.1, “Writing the Freescale Semiconductor 0 0 ...
Page 75
... SEC[1:0] module is unsecured using backdoor key access, the SEC bits are forced to 10. KEYEN[1:0] 1 Preferred KEYEN state to disable Backdoor Key Access. SEC[1:0] 1 Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Freescale Semiconductor RNV5 RNV4 RNV3 Figure 2-5 ...
Page 76
... Command buffer empty interrupt disabled interrupt will be requested whenever the CBEIF flag (see is set Figure 2-6. RESERVED1 KEYACC Section 2.3.2.2) is set to the enabled state. Table 2-8. FCNFG Field Descriptions Description Section 2.3.2.7, “Flash Status Register (FSTAT)”) MC9S12NE64 Data Sheet, Rev. 1 BKSEL Freescale Semiconductor ...
Page 77
... Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected FPHS[1:0] area as shown in Table Freescale Semiconductor Description Restrictions”). Table 2-9. FPROT Field Descriptions Description 2-11. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. ...
Page 78
... Unpaged Paged Address Range Address Range 0x4000-0x41FF 0x3E: 0x8000-0x81FF 0x4000-0x43FF 0x3E: 0x8000-0x83FF 0x4000-0x47FF 0x3E: 0x8000-0x87FF 0x4000-0x4FFF 0x3E: 0x8000-0x8FFF MC9S12NE64 Data Sheet, Rev. 1.1 1 Function Protected Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Protected Size 512 bytes 1 Kbyte 2 Kbytes 4 Kbytes Freescale Semiconductor ...
Page 79
... Flash array after reset, it can be changed by the user. This protection scheme can be used by applications requiring re-programming in single-chip mode while providing as much protection as possible if re-programming is not required. Freescale Semiconductor Figure 2-8. Although the protection scheme is MC9S12NE64 Data Sheet, Rev. 1.1 Memory Map and Register Defi ...
Page 80
... PPAGE 0x3C-0x3D PPAGE 0x3E-0x3F Unprotected region Protected region not defined by FPLS, FPHS 80 FPHDIS=1 FPHDIS=0 FPLDIS=0 FPLDIS Figure 2-8. Flash Protection Scenarios MC9S12NE64 Data Sheet, Rev. 1.1 FPHDIS=0 FPLDIS Protected region with size defined by FPLS Protected region with size defined by FPHS Freescale Semiconductor ...
Page 81
... Flash Status Register (FSTAT) The FSTAT register defines the operational status of the module CCIF CBEIF W Reset Unimplemented or Reserved Figure 2-9. Flash Status Register (FSTAT - Normal Mode CCIF CBEIF W Reset Unimplemented or Reserved Figure 2-10. Flash Status Register (FSTAT - Special Mode) Freescale Semiconductor To Protection Scenario ...
Page 82
... FAIL verified as not erased). The FAIL flag is cleared by writing FAIL. Writing the FAIL flag has no effect on FAIL. 0 Flash operation completed without error. 1 Flash operation failed. 82 Table 2-14. FSTAT Field Descriptions Description MC9S12NE64 Data Sheet, Rev. 1.1 Figure 2-28). Freescale Semiconductor ...
Page 83
... Reset Unimplemented or Reserved All bits in the FCTL register are readable but are not writable. The FCTL register is loaded from the Flash Configuration Field byte at $FF0E during the reset sequence, indicated Figure 2-12. Freescale Semiconductor CMDB Table 2-15. FCMD Field Descriptions ...
Page 84
... FADDR registers will contain the mapped MCU address written. 2.3.2.11 Flash Data Registers (FDATA) The FDATAHI and FDATALO registers are the Flash data registers Reset Unimplemented or Reserved Figure 2-15. Flash Data High Register (FDATAHI) 84 Table 2-17. FCTL Field Descriptions Description FADDRHI FADDRLO FDATAHI MC9S12NE64 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 85
... All bits read 0 and are not writable. 2.3.2.13 RESERVED3 This register is reserved for factory testing and is not accessible Reset Unimplemented or Reserved All bits read 0 and are not writable. 2.3.2.14 RESERVED4 This register is reserved for factory testing and is not accessible. Freescale Semiconductor FDATALO Figure 2-17. RESERVED2 ...
Page 86
... How to write the FCLKDIV register. 2. Command write sequences used to program, erase, and verify the Flash memory. 3. Valid Flash commands. 4. Effects resulting from illegal Flash command write sequences or aborting Flash operations Figure 2-19. RESERVED4 Figure 2-20. RESERVED5 MC9S12NE64 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 87
... Flash memory cells. If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. Flash commands will not be executed if the FCLKDIV register has not been written to. Freescale Semiconductor ( ) 200 ⁄ ...
Page 88
... OSCILLATOR NO CLOCK > 12.8 MHZ? YES PRDIV8=1 PRDCLK=oscillator_clock PRDCLK=oscillator_clock/8 NO PRDCLK[MHz]*(5+Tbus[µs]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) YES FCLK=(PRDCLK)/(1+FDIV[5:0]) YES 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15 MHz ? NO FDIV[5:0] > ALL COMMANDS IMPOSSIBLE MC9S12NE64 Data Sheet, Rev. 1.1 END Freescale Semiconductor ...
Page 89
... A command write sequence can be aborted prior to clearing the CBEIF flag by writing the CBEIF flag and will result in the ACCERR flag being set. Freescale Semiconductor (FSTAT)”) and the CBEIF flag must be tested to Section 2.4.1.3.1, “Erase Verify Section 2.4.1.3.2, “Data Compress Section 2.4.1.3.3, “ ...
Page 90
... The Flash sector must not be considered erased if the ACCERR flag is set upon Abort command completion. A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 90 Function on Flash Memory CAUTION MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 91
... Access Error Check Bit Polling for Command Completion Check Figure 2-22. Example Erase Verify Command Flow Freescale Semiconductor no yes Write: Register FCLKDIV Write: Flash Block Address and Dummy Data NOTE: command write sequence Write: Register FCMD aborted by writing 0x00 to Erase Verify Command 0x05 FSTAT register ...
Page 92
... Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid signature, the Flash sector must be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased. 92 NOTE MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 93
... Error Check Bit Polling for Command Completion Check Signature Compared to Known Value Figure 2-23. Example Data Compress Command Flow Freescale Semiconductor no yes Write: Register FCLKDIV Write: Flash address to start compression and number of word addresses to compress (max 16,384) NOTE: command write sequence ...
Page 94
... PVIOL Clear bit PVIOL 0x20 Set? no Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit yes CBEIF Set? no Bit no CCIF Read: Register FSTAT Set? yes EXIT MC9S12NE64 Data Sheet, Rev. 1.1 Figure 2-24. yes Next Write? no Freescale Semiconductor ...
Page 95
... Error Check Address, Data, Command Buffer Empty Check Bit Polling for Command Completion Check Figure 2-25. Example Sector Erase Command Flow Freescale Semiconductor no Write: Register FCLKDIV NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register ...
Page 96
... Write: Register FSTAT PVIOL Clear bit PVIOL 0x20 Set? no Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit yes CBEIF Set? no Bit no CCIF Read: Register FSTAT Set? yes EXIT MC9S12NE64 Data Sheet, Rev. 1.1 yes Next Write? no Freescale Semiconductor ...
Page 97
... ACCERR flag, if set. The sector erase abort command must be used sparingly because a sector erase operation that is aborted counts as a complete program/erase cycle. Freescale Semiconductor NOTE NOTE MC9S12NE64 Data Sheet, Rev. 1.1 Functional Description Section 2.4.1.1, “ ...
Page 98
... CCIF Command Set? Completion Check yes Bit Access ACCERR Error Check Set? no EXIT Sector Erase Completed MC9S12NE64 Data Sheet, Rev. 1.1 no Read: Register FSTAT no Read: Register FSTAT yes Write: Register FSTAT Clear bit ACCERR 0x10 EXIT Sector Erase Aborted Freescale Semiconductor ...
Page 99
... If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 2.3.2.7, “Flash Status Register Freescale Semiconductor Section 2.4.1.3.6, “Sector Erase Abort Section 2.3.2.7, “Flash Status Register MC9S12NE64 Data Sheet, Rev. 1.1 Functional Description Section 2.5.2, “ ...
Page 100
... If the KEYEN[1:0] bits are in the enabled state (see 100 Sequence”). NOTE can be executed. Section 2.3.2.2, “Flash Security Register Section 2.3.2.2, “Flash Security Register MC9S12NE64 Data Sheet, Rev. 1.1 (FSEC)”) and the Freescale Semiconductor ...
Page 101
... Flash protection register not possible to unsecure the MCU in special single-chip mode by using the backdoor key access sequence via the background debug mode (BDM). Freescale Semiconductor Section 2.3.2.2, “Flash Security Register MC9S12NE64 Data Sheet, Rev. 1.1 Flash Module Security (FSEC)” ...
Page 102
... Table 2-1: Section 2.3.2.5). Section 2.3.2.9). Section 2.3.2.2). Table 2-19. Flash Interrupt Sources Interrupt Flag CBEIF (FSTAT register) CBEIE (FCNFG register) CCIF (FSTAT register) CCIE (FCNFG register) MC9S12NE64 Data Sheet, Rev. 1.1 Local Enable Global (CCR) Mask I Bit I Bit Freescale Semiconductor ...
Page 103
... CBEIF CBEIE CCIF CCIE For a detailed description of the register bits, refer to (FCNFG)” and Section 2.3.2.7, “Flash Status Register Freescale Semiconductor NOTE Figure 2-28. Flash Command Interrupt Request Figure 2-28. Flash Interrupt Implementation Section 2.3.2.4, “Flash Configuration Register (FSTAT)”. ...
Page 104
... Chapter 2 64 Kbyte Flash Module (S12FTS64KV3) 104 MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 105
... L connected to EPHY module Each I/O pin can be configured by several registers: Input/output selection, drive strength reduction, enable and select of pull resistors, interrupt enable and status flags. The implementation of the port integration module is device dependent. Freescale Semiconductor MC9S12NE64 Data Sheet, Rev. 1.1 105 ...
Page 106
... SPI_MISO PS4 SPI_MOSI PS5 SPI_SCK PS6 SPI_SS PS7 BKGD XIRQ PE0 IRQ PE1 R/W PE2 PE3 ECLK PE4 IPIPE0/MODA PE5 IPIPE1/MODB PE6 NOACC PE7 XADDR14 PK0 XADDR15 PK1 XADDR16 PK2 XADDR17 PK3 XADRR18 PK4 XADDR19 PK5 PK6 XCS PK7 Freescale Semiconductor ...
Page 107
... GPIO PE2 R/W / GPIO PE1 IRQ/GPI PE0 XIRQ/GPI Freescale Semiconductor Description Refer the MEBI block description chapter. Refer the MEBI block description chapter. Refer the MEBI block description chapter. MC9S12NE64 Data Sheet, Rev. 1.1 External Signal Description Pin Function after Reset ...
Page 108
... Key board wake up Interrupts or General-purpose I/O MII Transmit Enable Key board wake up Interrupts or General-purpose I/O MII Transmit Clock Key board wake up Interrupts or General-purpose I/O MII Transmit Data Key board wake up Interrupts or General-purpose I/O MC9S12NE64 Data Sheet, Rev. 1.1 Pin Function after Reset GPIO GPIO Freescale Semiconductor ...
Page 109
... GPIO PL[1] LNKLED GPIO PL[0] ACTLED GPIO Freescale Semiconductor Description Serial Clock Line bidirectional pin of IIC module Key board wake up Interrupt or General-purpose I/O Serial Data Line bidirectional pin of IIC module Key board wake up Interrupt or General-purpose I/O MII Collision Key board wake up Interrupt or General-purpose I/O ...
Page 110
... Serial Communication Interface 0 transmit pin General-purpose I/O Serial Communication Interface 0 receive pin General-purpose I/O Standard Timer1 Channels General-purpose I/O Table 3-2. PIM Module Memory Map Use MC9S12NE64 Data Sheet, Rev. 1.1 Pin Function after Reset GPIO GPIO Access R/W R R/W R/W R/W R/W Freescale Semiconductor ...
Page 111
... Port L Reduced Drive Register (RDRL) $2C Port L Pull Device Enable Register (PERL) $2D Port L Polarity Select Register (PPSL) $2E Port L Wired-Or Mode Register (WOML) $2F-$3F Reserved Freescale Semiconductor MC9S12NE64 Data Sheet, Rev. 1.1 Memory Map and Register Descriptions — R/W R R/W R/W R/W R/W R/W — ...
Page 112
... Disabled Pull Up Disabled Pull Down Disabled Disabled Falling edge Disabled Rising edge Pull Up Falling edge Pull Down Rising edge Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Falling edge Disabled Rising edge Disabled Falling edge Disabled Rising edge Freescale Semiconductor ...
Page 113
... Data Direction Register (DDRT) Module Base + $2 Bit 7 6 Read: DDRT7 DDRT6 Write: Reset Reserved or unimplemented Figure 3-4. Port T Data Direction Register (DDRT) Freescale Semiconductor PTT5 PTT4 IOC5 IOC4 0 0 — Figure 3-2. Port T I/O Register (PTT ...
Page 114
... This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. RDRT[7:4] — Reduced Drive Port Associated pin drives at about 1/3 of the full drive strength Full drive strength at output. 114 RDRT5 RDRT4 0 0 — MC9S12NE64 Data Sheet, Rev. 1 Bit — — — Freescale Semiconductor ...
Page 115
... PPST[7:4] — Pull Select Port pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. Freescale Semiconductor ...
Page 116
... SCI1_TXD SCI1_RXD SCI0_TXD SCI0_RXD Figure 3-8. Port S I/O Register (PTS PTIS5 PTIS4 PTIS3 — — — Figure 3-9. Port S Input Register (PTIS) MC9S12NE64 Data Sheet, Rev. 1 Bit 0 PTS2 PTS1 PTS0 — — — Bit 0 PTIS2 PTIS1 PTIS0 — — — Freescale Semiconductor ...
Page 117
... Read: RDRS7 RDRS6 Write: Reset Figure 3-11. Port S Reduced Drive Register (RDRS) Read:Anytime. Write:Anytime. This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. Freescale Semiconductor DDRS5 DDRS4 DDRS3 RDRS5 ...
Page 118
... A pull-up device is connected to the associated port S pin, if enabled by the associated bit in PERS register and if the port is used as input or as wired-or output. 118 PERS5 PERS4 PERS3 PPSS5 PPSS4 PPSS3 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 PERS2 PERS1 PERS0 Bit 0 PPSS2 PPSS1 PPSS0 Freescale Semiconductor ...
Page 119
... The EMAC MII external interface takes precedence over general-purpose I/O function if the EMAC module is enabled in external PHY mode. If the EMAC is enabled PG[6:0] pins become inputs MII_RXER, MII_RXDV, MII_RXCLK, MII_RXD[3:0]. Please refer to the EMAC block description chapter for details. Freescale Semiconductor ...
Page 120
... Due to internal synchronization circuits, it can take bus cycles until the correct value is read on PTG or PTIG registers, when changing the DDRG register. 120 PTIG5 PTIG4 PTIG3 — — — Figure 3-16. Port G Input Register (PTIG DDRG5 DDRG4 DDRG3 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 PTIG2 PTIG1 PTIG0 — — — Bit 0 DDRG2 DDRG1 DDRG0 Freescale Semiconductor ...
Page 121
... PERG[7:0] — Pull Device Enable Port Either a pull-up or pull-down device is enabled Pull-up or pull-down device is disabled. 3.3.2.3.6 Polarity Select Register (PPSG) Module Base + $15 Bit 7 6 Read: PPSG7 PPSG6 Write: Reset Figure 3-20. Port G Polarity Select Register (PPSG) Freescale Semiconductor RDRG5 RDRG4 RDRG3 PERG5 PERG4 PERG3 ...
Page 122
... PPSG register. To clear this flag, write a “1” to the corresponding bit in the PIFG register. Writing a “0” has no effect. 122 PIEG5 PIEG4 PIEG3 PIFG5 PIFG4 PIFG3 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 PIEG2 PIEG1 PIEG0 Bit 0 PIFG2 PIFG1 PIFG0 Freescale Semiconductor ...
Page 123
... Input Register (PTIH) Module Base + $19 Bit 7 6 Read: 0 PTIH6 Write: Reset: — — = Reserved or unimplemented Read:Anytime. Write:Never, writes to this register have no effect. Freescale Semiconductor PTH5 PTH4 PTH3 KWH Figure 3-23. Port H I/O Register (PTH PTIH5 PTIH4 PTIH3 — ...
Page 124
... RDRH[6:0] — Reduced Drive Port Associated pin drives at about 1/3 of the full drive strength Full drive strength at output. 124 DDRH5 DDRH4 DDRH3 RDRH5 RDRH4 RDRH3 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 DDRH2 DDRH1 DDRH0 Bit 0 RDRH2 RDRH1 RDRH0 Freescale Semiconductor ...
Page 125
... PERH and if the port is used as input Falling edge on the associated port H pin sets the associated flag bit in the PIFH register.A pull-up device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. Freescale Semiconductor ...
Page 126
... Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag active edge pending. Writing a “0” has no effect. 126 PIEH5 PIEH4 PIEH3 PIFH5 PIFH4 PIFH3 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 PIEH2 PIEH1 PIEH0 Bit 0 PIFH2 PIFH1 PIFH0 Freescale Semiconductor ...
Page 127
... PTIJ6 Write: Reset: — — = Reserved or unimplemented Read:Anytime. Write: writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. Freescale Semiconductor PTJ3 MII_COL — — — ...
Page 128
... RDRJ[7:6][3:0] — Reduced Drive Port Associated pin drives at about 1/3 of the full drive strength Full drive strength at output. 128 DDRJ3 — — RDRJ3 — — 0 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 DDRJ2 DDRJ1 DDRJ0 Bit 0 RDRJ2 RDRJ1 RDRJ0 Freescale Semiconductor ...
Page 129
... PERJ and if the port is used as input Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. Freescale Semiconductor ...
Page 130
... Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag active edge pending. Writing a “0” has no effect. 130 PIEJ3 — — PIFJ3 — — 0 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 PIEJ2 PIEJ1 PIEJ0 Bit 0 PIFJ2 PIFJ1 PIFJ0 Freescale Semiconductor ...
Page 131
... Write: Reset: — — = Reserved or unimplemented Read:Anytime. Write:Never, writes to this register have no effect. This register always reads back the status of the associated pins. This also can be used to detect overload or short circuit conditions on output pins. Freescale Semiconductor PTL5 PTL4 PTL3 COLLED DUPLED ...
Page 132
... RDRL[6:0] — Reduced Drive Port Associated pin drives at about 1/3 of the full drive strength Full drive strength at output. 132 DDRL5 DDRL4 DDRL3 RDRL5 RDRL4 RDRL3 MC9S12NE64 Data Sheet, Rev. 1 Bit 0 DDRL2 DDRL1 DDRL0 Bit 0 RDRL2 RDRL1 RDRL0 Freescale Semiconductor ...
Page 133
... A pull-down device is connected to the associated port L pin, if enabled by the associated bit in register PERL and if the port is used as input pull-up device is connected to the associated port L pin, if enabled by the associated bit in register PERL and if the port is used as input or as wired-or output. Freescale Semiconductor ...
Page 134
... If the data direction register bits are set to 1, the contents of the I/O register is returned. This is independent of any other configuration (Figure 3.4.2 Input Register This is a read-only register and always returns the value of the pin Data direction register 134 WOML5 WOML4 WOML3 3-46). MC9S12NE64 Data Sheet, Rev. 1 Bit 0 WOML2 WOML1 WOML0 (Figure 3-46). Freescale Semiconductor ...
Page 135
... Port T This port is associated with the standard Timer. In all modes, port T pins PT[7:4] can be used for either general-purpose I/O or standard timer I/O. During reset, port T pins are configured as high-impedance inputs. Freescale Semiconductor PTI ...
Page 136
... Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set t pign t pval Figure 3-47. Interrupt Glitch Filter on Port G, H, and J (PPS=0) 136 (Figure 3-48) shorter than a specified time from generating an MC9S12NE64 Data Sheet, Rev. 1.1 (Figure 3-47 and Freescale Semiconductor ...
Page 137
... Port J pins PJ[7:6] can be used either for general-purpose I/O or with the IIC subsystem. Port J pins PJ[3:0] can be used either for general-purpose I/O or with the EMAC subsystems. Further the Keypad Wake-Up function is implemented on pins H[6:0]. Port J offers the same interrupt features as on port G. Freescale Semiconductor Table 3-4. Pulse Detection Criteria Mode STOP ...
Page 138
... The reset values of all registers are given in 3.5.1 Reset Initialization All registers including the data registers get set/reset asynchronously. properties after reset initialization. 138 Section 3.3, “Memory Map and Register MC9S12NE64 Data Sheet, Rev. 1.1 Descriptions.” Table 3-5 summarizes the port Freescale Semiconductor ...
Page 139
... MCU level. 3.6.2 Recovery from Stop The PIM_9NE64 can generate wake-up interrupts from stop on port G, H, and J. For other sources of external interrupts please refer to the respective block description chapter. Freescale Semiconductor Table 3-5. Port Reset State Summary Reset States Wired-Or Pull Mode Red ...
Page 140
... Chapter 3 Port Integration Module (PIM9NE64V1) 140 MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 141
... System reset generation from the following possible sources: — Power-on reset — Low voltage reset Refer to the device overview section for availability of this feature. — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12NE64 Data Sheet, Rev. 1.1 141 ...
Page 142
... Self-clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 4.1.3 Block Diagram Figure 4-1 shows a block diagram of the CRGV4. 142 MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 143
... PLL. Refer to the device overview chapter for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be tied DDPLL Freescale Semiconductor Power-on Reset 1 Low Voltage Reset CRG Reset ...
Page 144
... CTCTL is intended for factory test purposes only. 144 CS MCU RS XFC Figure 4-2. PLL Loop Filter Connections Table 4-1. CRGV4 Memory Map Use MC9S12NE64 Data Sheet, Rev. 1.1 V DDPLL CP Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Freescale Semiconductor ...
Page 145
... REFDV CTFLG CRGFLG R RTIF W CRGINT R RTIE W CLKSEL R PLLSEL W PLLCTL R CME W RTICTL COPCTL R WCOP W FORBYP CTCTL Freescale Semiconductor NOTE SYN5 SYN4 REFDV3 PORF LVRF LOCKIF 0 0 LOCKIE PSTP SYSWAI ROAWAI PLLON AUTO ACQ RTR6 RTR5 RTR4 0 0 RSBCK Unimplemented or Reserved Figure 4-3. CRG Register Summary MC9S12NE64 Data Sheet, Rev. 1.1 Memory Map and Register Defi ...
Page 146
... Write to this register initializes the lock detector bit and the track detector bit. 146 Bit 6 Bit 5 Bit 4 = Unimplemented or Reserved ( SYNR = ---------------------------------- - PLLCLK 2xOSCCLKx ( REFDV NOTE SYN5 SYNR SYN3 NOTE MC9S12NE64 Data Sheet, Rev. 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 ). SCM ) + SYN2 SYN1 0 0 Freescale Semiconductor 0 0 SYN0 0 ...
Page 147
... This register is reserved for factory testing of the CRGV4 module and is not available in normal modes Reset Unimplemented or Reserved Figure 4-6. CRG Reserved Register (CTFLG) Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes Writing to this register when in special mode can alter the CRGV4 functionality. Freescale Semiconductor REFDV3 NOTE ...
Page 148
... Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode. TRACK Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status. 148 LOCK LVRF LOCKIF Note Figure 4-7. CRG Flag Register (CRGFLG) Table 4-2. CRGFLG Field Descriptions Description MC9S12NE64 Data Sheet, Rev. 1 TRACK SCM SCMIF Freescale Semiconductor ...
Page 149
... Interrupt will be requested whenever RTIF is set. 4 Lock Interrupt Enable Bit LOCKIE 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 Self-Clock Mode Interrupt Enable Bit SCMIE 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set. Freescale Semiconductor Description . SCM LOCKIE 0 ...
Page 150
... Core Stops in Wait Mode Bit — Write: anytime CWAI 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode. 150 Figure 4- SYSWAI ROAWAI PLLWAI Table 4-4. CLKSEL Field Descriptions Description MC9S12NE64 Data Sheet, Rev. 1.1 for details on the effect of each bit CWAI RTIWAI COPWAI 0 0 Freescale Semiconductor 0 0 ...
Page 151
... Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. 4 Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect. ACQ 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. Freescale Semiconductor Description AUTO ...
Page 152
... Table 4-6. RTICTL Field Descriptions Description Table 4-7 shows all possible divide values selectable by the RTICTL register. The MC9S12NE64 Data Sheet, Rev. 1.1 Section 4.5.1, “Clock Monitor Reset”). Section 4.4.7.2, “Self-Clock Mode”). RTR2 RTR1 RTR0 Table Freescale Semiconductor 4-7. ...
Page 153
... OFF* 1100 (÷ 13) OFF* 1101 (÷14) OFF* 1110 (÷15) OFF* 1111 (÷ 16) * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor Table 4-7. RTI Frequency Divide Rates RTR[6:4] = 001 010 011 ...
Page 154
... ARMCOP register) 154 Table 4-8. COPCTL Field Descriptions Description Table 4-9. COP Watchdog Rates OSCCLK CR1 CR0 Cycles to Time Out 0 0 COP disabled MC9S12NE64 Data Sheet, Rev. 1 CR2 CR1 0 0 Table 4-9 Table 4-9). The COP Freescale Semiconductor 0 CR0 0 shows ...
Page 155
... Writing to this register when in special test modes can alter the CRG’s functionality Reset Unimplemented or Reserved Read: always read 0x0080 except in special modes Write: only in special modes Freescale Semiconductor NOTE Figure 4-13. Reserved Register (FORBYP) NOTE 5 ...
Page 156
... The PLL can change between acquisition and tracking modes either automatically or manually. 156 Bit 5 Bit 4 Bit Figure 4-15. ARMCOP Register Diagram [ SYNR × × = PLLCLK 2 OSCCLK ---------------------------------- - [ REFDV CAUTION MC9S12NE64 Data Sheet, Rev. 1 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 157
... The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor REFERENCE REFDV <3:0> ...
Page 158
... The following conditions apply when in sys MC9S12NE64 Data Sheet, Rev. 1.1 , and is clear when trk , and is cleared Lock . ) before acq ) before selecting the PLLCLK al Freescale Semiconductor ...
Page 159
... PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum Freescale Semiconductor PLLSEL or SCM 1 ...
Page 160
... A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See 1. VCO clock cycles are generated by the PLL when running at minimum frequency f 160 1 is called check window. Figure 4-19 MC9S12NE64 Data Sheet, Rev. 1 example. . SCM Freescale Semiconductor ...
Page 161
... Figure 4-20. Sequence for Clock Quality Check Remember that in parallel to additional actions caused by self-clock mode or clock monitor reset check the OSCCLK signal Clock Monitor Reset will always set the SCME bit to logical’1’ Freescale Semiconductor check window 4096 4095 osc ok Figure 4-19 ...
Page 162
... Reset).” The COP runs with a gated OSCCLK (see COP”). Three control bits in the COPCTL register allow selection MC9S12NE64 Data Sheet, Rev. 1.1 ) and an active VREG CR[2:0] 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 COP TIMEOUT Section 4.5.2, Freescale Semiconductor ...
Page 163
... Self-Clock Mode The VCO has a minimum operating frequency failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO Freescale Semiconductor RTI”). At the end of the RTI time-out period the . WAIT(RTIWAI), RTI enable ÷ ...
Page 164
... MC9S12NE64 Data Sheet, Rev. 1.1 Section 4.4.4, “Clock Quality COPWAI ROAWAI — — — — — — — — stopped — 1 — reduced Figure 4-23). Depending on Freescale Semiconductor ...
Page 165
... Core req’s Wait Mode. no PLLWAI=1 ? yes CWAI or Clear SYSWAI=1 PLLSEL, ? Disable PLL yes Disable core clocks Figure 4-23. Wait Mode Entry/Exit Sequence Freescale Semiconductor no no SYSWAI=1 ? yes Disable Enter system clocks Wait Mode Wait Mode left due to external reset Exit Wait w. ext.RESET no Exit Wait w ...
Page 166
... If wait mode is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 4-11 summarizes the outcome of a clock loss while in wait mode. 166 MC9S12NE64 Data Sheet, Rev. 1.1 Section 4.4.4, “Clock Freescale Semiconductor ...
Page 167
... Continue to perform additional Clock Quality Checks until OSCCLK or an External RESET is applied. – Exit Wait Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK Freescale Semiconductor CRG Actions while in Wait Mode. is o.k. again. is o.k.again. ...
Page 168
... A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit. 168 CRG Actions ) as system clock, SCM MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 169
... Wake-up from pseudo-stop is the same as wake-up from wait mode. There are also three different scenarios for the CRG to restart the MCU from pseudo-stop mode: • External reset • Clock monitor fail • Wake-up interrupt Freescale Semiconductor Core req’s Stop Mode. Clear PLLSEL, Disable PLL Wait Mode left Enter ...
Page 170
... MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 4-12 summarizes the outcome of a clock loss while in pseudo-stop mode. 170 MC9S12NE64 Data Sheet, Rev. 1.1 Section 4.4.4, “Clock Freescale Semiconductor ...
Page 171
... External RESET is applied. – Exit Pseudo-Stop Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. Freescale Semiconductor CRG Actions MC9S12NE64 Data Sheet, Rev. 1.1 Functional Description ) as system clock SCM ...
Page 172
... The reset values of registers and signals are provided in 172 CRG Actions SCM Checker”). After completing the clock quality check Checker”). If the clock quality check is successful, the NOTE Section 4.3, “Memory Map and Register MC9S12NE64 Data Sheet, Rev. 1 system clock, Freescale Semiconductor ...
Page 173
... External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. Freescale Semiconductor Table 4-13. Refer to the device overview chapter for related Table 4-13 ...
Page 174
... CRG drives RESET pin low RESET pin released ) ( 128+n cycles 64 cycles with n being possibly min 3 / max 6 SYSCLK cycles depending not on internal running synchronization delay Figure 4-25. RESET Timing MC9S12NE64 Data Sheet, Rev. 1 possibly RESET driven low externally Section 4.3, Freescale Semiconductor ...
Page 175
... RESET Internal POR Internal RESET Figure 4-26. RESET Pin Tied to V RESET Internal POR Internal RESET Figure 4-27. RESET Pin Held Low Externally Freescale Semiconductor to the MCU has reached a certain level and asserts DD Clock Quality Check (no Self-Clock Mode 128 SYSCLK 64 SYSCLK ...
Page 176
... Table Table 4-15. CRG Interrupt Vectors CCR Local Enable Mask I bit CRGINT (RTIE) I bit CRGINT (LOCKIE) I bit CRGINT (SCMIE) Section 4.4.4, “Clock Quality MC9S12NE64 Data Sheet, Rev. 1.1 4-15. Refer to the device overview Checker.” If the clock monitor Freescale Semiconductor ...
Page 177
... Full swing Pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequency operation and harsh environments 5.2 External Signal Description This section lists and describes the signals that connect off chip. Freescale Semiconductor 2.5 V (nominal) supply rail MC9S12NE64 Data Sheet, Rev. 1.1 177 ...
Page 178
... XTAL is the output of the crystal oscillator amplifier. All the MCU internal system clocks are derived from the EXTAL input frequency. In full stop mode (PSTP = 0) the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier The Crystal circuit is changed from standard. ...
Page 179
... Pierce oscillator/external clock circuitry is used. The XCLKS signal is sampled during reset with the rising edge of RESET. sampled XCLKS signal. Refer to the device overview chapter for polarity of the XCLKS pin. XCLKS 0 1 Freescale Semiconductor Crystal or Ceramic RB Resonator RS* CMOS-Compatible ...
Page 180
... Interrupts OSCV2 contains a clock monitor, which can trigger an interrupt or reset. The control bits and status bits for the clock monitor are described in the CRG block description chapter. 180 and V power supply pins. DDPLL SSPLL MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 181
... Timer is off because clocks are stopped. Freeze: Timer counter keep on running, unless TSFRZ in TSCR (0x0006) is set to 1. Wait: Counters keep on running, unless TSWAI in TSCR (0x0006) is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR (0x0006) is cleared to 0. Freescale Semiconductor MC9S12NE64 Data Sheet, Rev. 1.1 181 ...
Page 182
... Counter Registers Channel 4 Channel 5 Channel 6 Channel 7 16-bit Pulse accumulator Figure 6-1. TIM16B4CV1 Block Diagram MC9S12NE64 Data Sheet, Rev. 1.1 Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Freescale Semiconductor IOC4 IOC5 IOC6 IOC7 ...
Page 183
... CLK1 CLK0 Prescaled clock (PCLK) Interrupt Figure 6-2. 16-Bit Pulse Accumulator Block Diagram PTn Edge detector Freescale Semiconductor TIMCLK (Timer clock) 4:1 MUX Clock select (PAMOD) PACNT 16-bit Main Timer TCn Input Capture Reg. Figure 6-3. Interrupt Flag Setting MC9S12NE64 Data Sheet, Rev. 1.1 ...
Page 184
... IOC4 — Input Capture and Output Compare Channel 4 Pin This pin serves as input capture or output compare for channel 4. For the description of interrupts see 184 OM7 OL7 OC7M7 NOTE of this document. NOTE Section 6.6, “Interrupts”. MC9S12NE64 Data Sheet, Rev. 1.1 PAD Freescale Semiconductor ...
Page 185
... Reserved 0x002D Timer Test Register (TIMTST) 0x002E – 0x002F Reserved 1 Always read 0x0000. Freescale Semiconductor Table 6-1. TIM16B4CV1 Memory Map Use MC9S12NE64 Data Sheet, Rev. 1.1 Memory Map and Register Definition Table 6-1. The address listed for each ...
Page 186
... MC9S12NE64 Data Sheet, Rev. 1 IOS3 IOS2 IOS1 FOC3 FOC2 FOC1 OC7M3 OC7M2 OC7M1 OC7M0 OC7D3 OC7D2 OC7D1 OC7D0 TCNT10 TCNT9 TCNT8 TCNT3 TCNT2 TCNT1 TCNT0 TOV3 TOV2 TOV1 OM5 OL5 OM4 EDG5B EDG5A EDG4B EDG4A Freescale Semiconductor Bit 0 IOS0 0 FOC0 0 TOV0 OL4 0 ...
Page 187
... TCxH–TCxL R Bit 7 W 0x0020 R 0 PACTL W 0x0021 R 0 PAFLG W 0x0022 R PACNT15 PACNTH W 0x0023 R PACNT7 PACNTL W 0x0024–0x002F R Reserved W Figure 6-5. TIM16B4CV1 Register Summary (continued) Freescale Semiconductor C6I C5I C4I C6F C5F C4F Bit 14 Bit 13 Bit 12 Bit 6 Bit 5 Bit 4 PAEN PAMOD ...
Page 188
... IOS5 IOS4 Table 6-2. TIOS Field Descriptions Description FOC5 FOC4 Table 6-3. CFORC Field Descriptions Description MC9S12NE64 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 189
... Output Compare 7 Data — A channel 7 output compare can cause bits in the output compare 7 data register OC7D[7:4] to transfer to the timer port data register depending on the output compare 7 mask register. 6.3.2.5 Timer Count Register (TCNT TCNT15 TCNT14 W Reset 0 0 Figure 6-10. Timer Count Register High (TCNTH) Freescale Semiconductor OC7M5 OC7M4 Table 6-4. OC7M Field Descriptions Description ...
Page 190
... Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. 190 TCNT5 TCNT4 TCNT3 TSFRZ TFFCA Table 6-6. TSCR1 Field Descriptions Description MC9S12NE64 Data Sheet, Rev. 1 TCNT2 TCNT1 TCNT0 Freescale Semiconductor ...
Page 191
... Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. 6.3.2.8 Timer Control Register 1 (TCTL1 OM7 OL7 W Reset 0 0 Figure 6-14. Timer Control Register 1 (TCTL1) Read: Anytime Write: Anytime Freescale Semiconductor Description TOV5 TOV4 Table 6-7. TTOV Field Descriptions Description ...
Page 192
... Table 6-8. TCTL1/TCTL2 Field Descriptions Description Table 6-9. Compare Result Output Action OLx Action 0 Timer disconnected from output pin logic 1 Toggle OCx output line 0 Clear OCx output line to zero 1 Set OCx output line to one MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 193
... Table 6-10. TCTL3/TCTL4 Field Descriptions Field 7:0 Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector EDGnB circuits. EDGnA Table 6-11. Edge Detector Circuit Configuration EDGnB Freescale Semiconductor EDG6B EDG6A EDG5B Description EDGnA Configuration ...
Page 194
... Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the PR[2:0] Bus Clock as shown in 194 C5I C4I Table 6-12. TIE Field Descriptions Description TCRE Table 6-13. TSCR2 Field Descriptions Description Table 6-14. MC9S12NE64 Data Sheet, Rev. 1 PR2 PR1 PR0 Freescale Semiconductor ...
Page 195
... Clear a channel flag by writing one to it. When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared. Freescale Semiconductor Table 6-14. Timer Clock Selection PR1 ...
Page 196
... Read: Anytime 196 Table 6-16. TRLG2 Field Descriptions Description Bit 13 Bit 12 Bit Bit 5 Bit 4 Bit MC9S12NE64 Data Sheet, Rev. 1 Bit 10 Bit 9 Bit Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 197
... IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling edge on IOC7 sets the PAIF flag. 1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge on IOC7 sets the PAIF flag. 3:2 Clock Select Bits — Refer to CLK[1:0] Freescale Semiconductor NOTE PAMOD PEDGE ...
Page 198
... Table 6-19. Timer Clock Selection CLK0 Timer Clock 0 Use timer prescaler clock as timer counter clock 1 Use PACLK as input to timer counter clock 0 Use PACLK/256 as timer counter clock frequency 1 Use PACLK/65536 as timer counter clock frequency Figure 6-22. MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor ...
Page 199
... PAIF and in gated time accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set. Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006) is set. Freescale Semiconductor ...
Page 200
... PACNT13 PACNT12 PACNT11 PACNT5 PACNT4 PACNT3 NOTE MC9S12NE64 Data Sheet, Rev. 1 PACNT10 PACNT9 PACNT8 PACNT2 PACNT1 PACNT0 Freescale Semiconductor ...