MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1050

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1)
then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the
optimum target by:
If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the
ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written
to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR
flag in the ESTAT register will set.
1052
Program and erase command execution time will increase proportionally
with the period of EECLK. Because of the impact of clock synchronization
on the accuracy of the functional timings, programming or erasing the
EEPROM memory cannot be performed if the bus clock runs at less than 1
MHz. Programming or erasing the EEPROM memory with EECLK < 150
kHz should be avoided. Setting ECLKDIV to a value such that EECLK <
150 kHz can destroy the EEPROM memory due to overstress. Setting
ECLKDIV to a value such that (1/EECLK+Tbus) < 5 s can result in
incomplete programming or erasure of the EEPROM memory cells.
MC9S12XDP512 Data Sheet, Rev. 2.21
200 182
–
CAUTION
200 100
=
9%
Freescale Semiconductor