MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1101

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.4.3
The ACCERR flag will be set during the command write sequence if any of the following illegal steps are
performed, causing the command write sequence to immediately abort:
The ACCERR flag will not be set if any EEPROM register is read during a valid command write sequence.
The ACCERR flag will also be set if any of the following events occur:
If the EEPROM memory is read during execution of an algorithm (CCIF = 0), the read operation will
return invalid data and the ACCERR flag will not be set.
If the ACCERR flag is set in the ESTAT register, the user must clear the ACCERR flag before starting
another command write sequence (see
The PVIOL flag will be set after the command is written to the ECMD register during a command write
sequence if any of the following illegal operations are attempted, causing the command write sequence to
immediately abort:
If the PVIOL flag is set in the ESTAT register, the user must clear the PVIOL flag before starting another
command write sequence (see
Freescale Semiconductor
1. Writing to an EEPROM address before initializing the ECLKDIV register.
2. Writing a byte or misaligned word to a valid EEPROM address.
3. Starting a command write sequence while a sector erase abort operation is active.
4. Writing to any EEPROM register other than ECMD after writing to an EEPROM address.
5. Writing a second command to the ECMD register in the same command write sequence.
6. Writing an invalid command to the ECMD register.
7. Writing to an EEPROM address after writing to the ECMD register.
8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the ECMD
9. Writing a 0 to the CBEIF flag in the ESTAT register to abort a command write sequence.
1. Launching the sector erase abort command while a sector erase or sector modify operation is active
2. The MCU enters stop mode and a command operation is in progress. The operation is aborted
1. Writing the program command if the address written in the command write sequence was in a
2. Writing the sector erase command if the address written in the command write sequence was in a
3. Writing the mass erase command to the EEPROM memory while any EEPROM protection is
4. Writing the sector modify command if the address written in the command write sequence was in
register.
which results in the early termination of the sector erase or sector modify operation (see
Section 26.4.2.5, “Sector Erase Abort
immediately and any pending command is purged (see
protected area of the EEPROM memory.
protected area of the EEPROM memory.
enabled.
a protected area of the EEPROM memory.
Illegal EEPROM Operations
Section 26.3.2.6, “EEPROM Status Register
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 26.3.2.6, “EEPROM Status Register
Command”).
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2)
Section 26.5.2, “Stop
(ESTAT)”).
(ESTAT)”).
Mode”).
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