MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1196

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
29.3.2.4
The FCNFG register enables the Flash interrupts and gates the security backdoor writes.
CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not
writable in normal mode. KEYACC is only writable if KEYEN (see
Register (FSEC)”
1198
MRDS[1:0]
Reset
Reset
Field
6:5
W
W
R
R
CBEIE
Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash
array as shown in
Flash Configuration Register (FCNFG)
0
0
0
7
7
is set to the enabled state.
= Unimplemented or Reserved
= Unimplemented or Reserved
CCIE
0
0
6
6
1 Flash array reads will be sensitive to program margin.
2 Flash array reads will be sensitive to erase margin.
Figure 29-7. Flash Configuration Register (FCNFG)
Figure 29-6. Flash Test Mode Register (FTSTMOD)
Table
MRDS
MRDS[1:0]
Table 29-7. FTSTMOD Margin Read Settings
Table 29-6. FTSTMOD Field Descriptions
29-7.
00
01
10
11
KEYACC
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
Undefined
Undefined
0
0
4
4
Margin Read Setting
Description
Program Margin
Erase Margin
Normal
Normal
0
0
0
0
3
3
2
1
Section 29.3.2.2, “Flash Security
0
0
0
0
2
2
Freescale Semiconductor
0
0
0
0
1
1
0
0
0
0
0
0