MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1206

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
All bits read 0 and are not writable.
29.3.2.14 RESERVED4
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
29.4
29.4.1
Write operations are used to execute program, erase, erase verify, erase abort, and data compress
algorithms described in this section. The program and erase algorithms are controlled by a state machine
whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command
register, as well as the associated address and data registers, operate as a buffer and a register (2-stage
FIFO) so that a second command along with the necessary data and address can be stored to the buffer
while the first command is still in progress. This pipelined operation allows a time optimization when
programming more than one word on a specific row in the Flash block as the high voltage generation can
be kept active in between two programming commands. The pipelined operation also allows a
simplification of command launching. Buffer empty as well as command completion are signalled by flags
in the Flash status register with corresponding interrupts generated, if enabled.
The next sections describe:
1208
Reset
Reset
1. How to write the FCLKDIV register
2. Command write sequences to program, erase, erase verify, erase abort, and data compress
3. Valid Flash commands
4. Effects resulting from illegal Flash command write sequences or aborting Flash operations
W
W
R
R
operations on the Flash memory
Functional Description
Flash Command Operations
0
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
Figure 29-20. RESERVED3
Figure 29-21. RESERVED4
0
0
0
0
4
4
0
0
0
0
3
3
0
0
0
0
2
2
Freescale Semiconductor
0
0
0
0
1
1
0
0
0
0
0
0

Related parts for MC9S12XDT256CAA