MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1215

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29.4.2.2.1
The Flash module contains a 16-bit multiple-input signature register (MISR) to generate a 16-bit signature
based on selected Flash array data. The final 16-bit signature, found in the FDATA registers after the data
compress operation has completed, is based on the following logic equation which is executed on every
data compression cycle during the operation:
where MISR is the content of the internal signature register and DATA is the data to be compressed as
shown in
During the data compress operation, the following steps are executed:
Freescale Semiconductor
1. MISR is reset to 0xFFFF.
2. Initialized DATA equal to 0xFFFF is compressed into the MISR which results in the MISR
3. DATA equal to the selected Flash array data range is read and compressed into the MISR with
4. DATA equal to the selected Flash array data range is read and compressed into the MISR with
5. DATA equal to the contents of the MISR is compressed into the same MISR.
6. The contents of the MISR are written to the FDATA registers.
DATA[0]
containing 0x0001.
addresses incrementing.
addresses decrementing.
+
MISR[15:0] = Q[15:0]
+
Figure
= Exclusive-OR
>
D Q
M0
Data Compress Operation
29-25.
DATA[1]
MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0]
+
>
D Q
M1
+
DATA[2]
+
Figure 29-25. 16-Bit MISR Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
>
D Q
M2
+
DATA[3]
+
>
D Q
M3
DATA[4]
+
>
D Q
M4
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
+
DATA[5]
+
>
D Q
M5
...
DATA[15]
+
>
M15
D Q
Eqn. 29-1
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