MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 206

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 6 XGATE (S12XGATEV2)
6.5
6.5.1
XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see
S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which
specific interrupt requests these are and which channel ID they are assigned to is documented in Section
“Interrupts” of the SoC Guide.
6.5.2
There are three types of interrupt requests which can be triggered by the XGATE module:
All XGATE interrupts can be disabled by the XGIE bit in the XGATE module control register (XGMCTL,
see
6.6
The XGATE debug mode is a feature to allow debugging of application code.
6.6.1
In debug mode the RISC core will be halted and the following debug features will be enabled:
1. Only possible if MCU is unsecured
206
4. Channel interrupts
5. Software triggers
6. Software error interrupt
Section 6.3.1.1, “XGATE Control Register
For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector
(XGIF, see
set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to
the S12X_CPU when the XGATE has completed one of its tasks.
Software triggers are interrupt flags, which can be set and cleared by software (see
“XGATE Software Trigger Register
by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see
S12X_INT Section) and triggered by the XGATE software.
The software error interrupt signals to the S12X_CPU the detection of an error condition in the
XGATE application code (see
Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)
All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue
program execution with the modified register values.
Interrupts
Debug Mode
Incoming Interrupt Requests
Outgoing Interrupt Requests
Debug Features
Section 6.3.1.4, “XGATE Channel Interrupt Flag Vector
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 6.4.5, “Software Error
(XGSWT)”). They are typically used to trigger XGATE tasks
(XGMCTL)”).
Detection”).
(XGIF)”). These flags can be
Freescale Semiconductor
Section 6.3.1.5,
1

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