MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 212

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 6 XGATE (S12XGATEV2)
6.8.1.13
For load and store instructions (RS, RI) provides a variable offset in a register.
Examples:
6.8.1.14
[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case
of a byte access the index register will be incremented by one. In case of a word access it will be
incremented by two.
Examples:
6.8.1.15
[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In
case of a byte access the index register will be decremented by one. In case of a word access it will be
decremented by two.
Examples:
6.8.2
6.8.2.1
Any register can be loaded either with an immediate or from the address space using indexed addressing
modes.
The same set of modes is available for the store instructions
212
LDB
STW
LDB
STW
LDB
STW
LDL
LDW
LDB
STB
STW
Instruction Summary and Usage
Index Register plus Register Offset (IDR)
Index Register plus Register Offset with Post-increment (IDR+)
Index Register plus Register Offset with Pre-decrement (–IDR)
Load & Store Instructions
R4,(R1,R2)
R4,(R1,R2)
R4,(R1,R2+)
R4,(R1,R2+)
R4,(R1,-R2)
R4,(R1,-R2)
RD,#IMM8
RD,(RB,RI)
RD,(RB, RI+)
RS,(RB, RI)
RS,(RB, RI+)
MC9S12XDP512 Data Sheet, Rev. 2.21
; loads a byte from R1+R2 into R4
; stores R4 as a word to R1+R2
; loads a byte from R1+R2 into R4, R2+=1
; stores R4 as a word to R1+R2, R2+=2
; R2 -=1, loads a byte from R1+R2 into R4
; R2 -=2, stores R4 as a word to R1+R2
; loads an immediate 8 bit value to the lower byte of RD
; loads data using RB+RI as effective address
; loads data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation
; stores data using RB+RI as effective address
; stores data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation.
Freescale Semiconductor

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