MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 398

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
9.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
9.3.2.1
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
398
Reserved
ADR[7:1]
Reset
Field
Register
7:1
0
Name
IBAD
IBCR
IBSR
IBDR
IBFD
W
R
ADR7
Register Descriptions
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
IIC Address Register (IBAD)
0
7
W
W
W
W
W
R
R
R
R
R
= Unimplemented or Reserved
ADR7
ADR6
IBEN
Bit 7
IBC7
TCF
D7
0
6
Figure 9-3. IIC Bus Address Register (IBAD)
= Unimplemented or Reserved
ADR6
IBC6
IAAS
IBIE
Figure 9-2. IIC Register Summary
D6
Table 9-1. IBAD Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
6
ADR5
0
5
MS/SL
ADR5
IBC5
IBB
D5
5
ADR4
0
4
Description
ADR4
Tx/Rx
IBC4
IBAL
D4
4
ADR3
0
3
ADR3
TXAK
IBC3
D3
3
0
ADR2
0
2
ADR2
IBC2
RSTA
SRW
D2
2
0
Freescale Semiconductor
ADR1
ADR1
IBC1
IBIF
D1
0
1
1
0
IBSWAI
RXAK
Bit 0
IBC0
D0
0
0
0
0

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