MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 426

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
1
2
3
4
5
6
7
8
9
10
10.3.2.2
The CANCTL1 register provides various control bits and handshake status information of the MSCAN
module as described below.
426
INITRQ
The MSCAN must be in normal mode for this bit to become set.
See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.
In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
the CPU enters wait (CSWAI = 1) or stop mode (see
“Operation in Stop
The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see
“MSCAN Receiver Interrupt Enable Register
The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
Not including WUPE, INITRQ, and SLPRQ.
TSTAT1 and TSTAT0 are not affected by initialization mode.
RSTAT1 and RSTAT0 are not affected by initialization mode.
SLPRQ
Field
1
0
6,7
5
Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving
mode (see
idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry
to sleep mode by setting SLPAK = 1 (see
cannot be set while the WUPIF flag is set (see
Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running — The MSCAN functions normally
1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle
Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see
Section 10.4.5.5, “MSCAN Initialization
synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1
(Section 10.3.2.2, “MSCAN Control Register 1
The following registers enter their hard reset state and restore their default values: CANCTL0
CANRIER
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the
error counters are not affected by initialization mode.
When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the
MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN
is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation
1 MSCAN in initialization mode
MSCAN Control Register 1 (CANCTL1)
Mode”)
10
Section 10.4.5.4, “MSCAN Sleep
Table 10-1. CANCTL0 Register Field Descriptions (continued)
, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
.
MC9S12XDP512 Data Sheet, Rev. 2.21
(CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.
Mode”). Any ongoing transmission or reception is aborted and
Section 10.4.5.2, “Operation in Wait
Section 10.3.2.2, “MSCAN Control Register 1
Mode”). The sleep mode request is serviced when the CAN bus is
Section 10.3.2.5, “MSCAN Receiver Flag Register
(CANCTL1)”).
Description
Mode” and
Freescale Semiconductor
(CANCTL1)”). SLPRQ
Section 10.4.5.3,
8
, CANRFLG
Section 10.3.2.6,
(CANRFLG)”).
9
,