MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 518

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12 Serial Peripheral Interface (S12SPIV4)
12.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
12.2.4
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
12.3
This section provides a detailed description of address space and registers used by the SPI.
12.3.1
The memory map for the SPI is given in
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
518
Reserved
Reserved
Reserved
Register
SPICR1
SPICR2
SPIDR
SPIBR
SPISR
Name
Memory Map and Register Definition
SS — Slave Select Pin
SCK — Serial Clock Pin
Module Memory Map
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
Bit 7
SPIE
SPIF
Bit 7
0
0
= Unimplemented or Reserved
SPPR2
SPE
6
0
0
6
Figure 12-2. SPI Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure
SPPR1
SPTEF
SPTIE
5
0
5
12-2. The address listed for each register is the sum of a
MODFEN
SPPR0
MSTR
MODF
4
4
BIDIROE
CPOL
3
0
0
3
CPHA
SPR2
2
0
0
2
Freescale Semiconductor
SPISWAI
SSOE
SPR1
1
0
1
LSBFE
SPC0
SPR0
Bit 0
Bit 0
0