MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 559

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2
This section describes all the VREG_3V3 registers and their individual bits.
14.3.2.1
The VREGHTCL is reserved for test purposes. This register should not be written.
14.3.2.2
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
Freescale Semiconductor
Reset
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
W
R
R
Register Descriptions
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
HT Control Register (VREGHTCL)
Control Register (VREGCTRL)
0
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
DDA
DDA
Figure 14-2. HT Control Register (VREGHTCL)
is above level V
is below level V
Figure 14-3. Control Register (VREGCTRL)
Table 14-3. VREGCTRL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
LVIA
LVID
and FPM.
or RPM or shutdown mode.
0
0
0
0
4
4
Description
0
0
0
0
3
3
Chapter 14 Voltage Regulator (S12VREG3V3V5)
LVDS
0
0
0
2
2
LVIE
0
0
0
1
1
LVIF
0
0
0
0
0
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