MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 614

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.1.2.2
17.1.3
Figure 1-1
17.2
The user is advised to refer to the SoC Guide for port configuration and location of external bus signals.
Some pins may not be bonded out in all implementations.
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EEPROM
FLASH
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
Single chip modes
In normal and special single chip mode the internal memory is used. External bus is not active.
Expanded modes
Address, data, and control signals are activated in normal expanded and special test modes when
accessing the external bus.
Emulation modes
External bus is active to emulate via an external tool the normal expanded or the normal single chip
mode.
EBI
External Signal Description
shows a block diagram of the MMC.
Block Diagram
Functional Modes
MMC
BDM
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 17-1. MMC Block Diagram
Address Decoder & Priority
Target Bus Controller
RAM
CPU
Peripherals
XGATE
Freescale Semiconductor
DBG