MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 678

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 18 Memory Mapping Control (S12XMMCV3)
Table 18-21
resources (internal) parameters.
18.4.2.4
18.4.2.4.1
The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and
FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the
BDM module . XGATE can access the FLASH in single chip modes, even when the MCU is secured. In
expanded modes, XGATE can not access the FLASH when MCU is secured.
The local address of the XGATE RAM access is translated to the global RAM address range. The XGATE
shares the RAM resource with the CPU and the BDM module . The local address of the XGATE FLASH
access is translated to the global address as shown in Figure 18-24. For the implemented memory spaces
and addresses please refer to
678
1
2
3
4
5
External RPAGE accesses in (NX, EX and ST)
External EPAGE accesses in (NX, EX and ST)
When ROMHM is set (see ROMHM in
on-chip memory block.
When the internal NVM is enabled (see ROMON in
the CS0 is not asserted in the space occupied by this on-chip memory block.
External PPAGE accesses in (NX, EX and ST)
shows the address boundaries of each chip select and the relationship with the implemented
XGATE Memory Map Scheme
Figure 18-23. Local to Implemented Global Address Mapping (Without GPAGE)
Chip Selects
Expansion of the XGATE Local Address Map
CS2
CS0
CS3
CS2
CS1
3
4
Table 18-21. Global Chip Selects Memory Space
Table 1-4
MC9S12XDP512 Data Sheet, Rev. 2.21
Bottom Address
and
0x00_0800
0x10_0000
0x14_0000
0x20_0000
0x40_0000
Table
Table
18-19) the CS2 is asserted in the space occupied by this
1-5.
Section 18.3.2.5, “MMC Control Register
0x13_FFFF minus EEPROMSIZE
0x7F_FFFF minus FLASHSIZE
0x0F_FFFF minus RAMSIZE
Top Address
0x1F_FFFF
0x3F_FFFF
Freescale Semiconductor
(MMCCTL1))
1
5
2