MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 721

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG
module is designed to help find.
LOOP
LOOP2
19.4.5.2.3
In detail mode, address and data for all memory and register accesses is stored in the trace buffer. In the
case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced.
This mode is intended to supply additional information on indexed, indirect addressing modes where
storing only the destination address would not provide all information required for a user to determine
where the code is in error. This mode also features information byte storage to the trace buffer, for each
address byte storage. The information byte indicates the size of access (word or byte), the type of access
(read or write).
When tracing CPU activity in detail mode, all cycles are traced except those when the CPU is either in a
free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide a snapshot
of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity occurring at the
time of the trace buffer entry. When tracing CPU activity alone in detail mode, the address range can be
limited to a range specified by the TRANGE bits in DBGTCR. This function uses comparators C and D
to define an address range inside which CPU activity should be traced (see
CPU activity can be restricted to register range accesses.
When tracing XGATE activity in detail mode, all cycles apart from opcode fetch and free cycles are stored
to the trace buffer. Additionally the CPU program counter is stored at the time of the XGATE trace buffer
entry to provide a snapshot of CPU activity.
19.4.5.3
The buffer can be used to trace either from CPU, from XGATE or from both sources. An “X” prefix
denotes information from the XGATE module, a “C” prefix denotes information from the CPU.
ADRH,ADRM,ADRL denote address high, middle and low byte respectively. INF bytes contain control
Freescale Semiconductor
INX
BRCLR
BRN*
NOP
DBNE
Trace Buffer Organization
In certain very tight loops, the source address will have already been fetched
again before the background comparator is updated. This results in the
source address being stored twice before further duplicate entries are
suppressed. This condition occurs with branch-on-bit instructions when the
branch is fetched by the first P-cycle of the branch or with loop-construct
instructions in which the branch is fetched with the first or second P cycle.
See examples below:
Detail Mode
CMPTMP,#$0c,LOOP
A,LOOP2
MC9S12XDP512 Data Sheet, Rev. 2.21
;1-byte instruction fetched by 1st P-cycle of BRCLR
;the BRCLR instruction also will be fetched by 1st P-cycle
;of BRCLR
; 2-byte instruction fetched by 1st P-cycle of DBNE
; 1-byte instruction fetched by 2nd P-cycle of DBNE
; this instruction also fetched by 2nd P-cycle of DBNE
NOTE
Chapter 19 S12X Debug (S12XDBGV2) Module
Table
19-10). Thus, the traced
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